2005-03-13 17:55:57 -05:00
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! Copyright (C) 2005 Slava Pestov.
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! See http://factor.sf.net/license.txt for BSD license.
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IN: assembler
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USING: errors kernel math memory words ;
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2005-03-14 13:20:57 -05:00
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! See the Motorola or IBM documentation for details. The opcode
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2005-03-20 19:05:57 -05:00
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! names are standard, and the operand order is the same as in
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! the docs, except a few differences, namely, in IBM/Motorola
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! assembler syntax, loads and stores are written like:
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!
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! stw r14,10(r15)
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!
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! In Factor, we write:
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!
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! 14 15 10 STW
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2005-03-14 13:20:57 -05:00
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2005-03-13 17:55:57 -05:00
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: insn ( operand opcode -- ) 26 shift bitor compile-cell ;
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: b-form ( bo bi bd aa lk -- n )
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>r 1 shift >r 2 shift >r 16 shift >r 21 shift
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r> bitor r> bitor r> bitor r> bitor ;
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: d-form ( d a simm -- n )
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HEX: ffff bitand >r 16 shift >r 21 shift r> bitor r> bitor ;
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2005-03-13 17:55:57 -05:00
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: i-form ( li aa lk -- n )
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>r 1 shift bitor r> bitor ;
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2005-03-19 21:23:21 -05:00
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: x-form ( s a b xo rc -- n )
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>r 1 shift >r 11 shift >r 16 shift >r 21 shift
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r> bitor r> bitor r> bitor r> bitor ;
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2005-03-13 17:55:57 -05:00
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: xfx-form ( d spr xo -- n )
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1 shift >r 11 shift >r 21 shift r> bitor r> bitor ;
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2005-03-19 21:23:21 -05:00
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: xo-form ( d a b oe xo rc -- n )
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>r 1 shift >r 10 shift >r 11 shift >r 16 shift >r 21 shift
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r> bitor r> bitor r> bitor r> bitor r> bitor ;
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2005-03-13 17:55:57 -05:00
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: ADDI d-form 14 insn ;
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: LI 0 rot ADDI ;
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: ADDIS d-form 15 insn ;
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: LIS 0 rot ADDIS ;
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2005-03-19 21:23:21 -05:00
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: ADD 0 266 0 xo-form 31 insn ;
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: SUBI neg ADDI ;
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2005-03-13 17:55:57 -05:00
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: ORI d-form 24 insn ;
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: SRAWI 824 0 x-form 31 insn ;
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: BL 0 1 i-form 18 insn ;
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2005-03-15 22:23:52 -05:00
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: B 0 0 i-form 18 insn ;
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2005-03-17 23:29:08 -05:00
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: BC 0 0 b-form 16 insn ;
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2005-03-19 00:30:49 -05:00
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: BEQ 12 2 rot BC ;
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2005-03-17 23:29:08 -05:00
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: BNE 4 2 rot BC ;
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2005-03-13 17:55:57 -05:00
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: BCLR 0 8 0 0 b-form 19 insn ;
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: BLR 20 BCLR ;
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2005-03-17 23:29:08 -05:00
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: BCLRL 0 8 0 1 b-form 19 insn ;
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: BLRL 20 BCLRL ;
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2005-03-19 00:30:49 -05:00
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: BCCTR 0 264 0 0 b-form 19 insn ;
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: BCTR 20 BCCTR ;
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2005-03-13 17:55:57 -05:00
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: MFSPR 5 shift 339 xfx-form 31 insn ;
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: MFLR 8 MFSPR ;
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2005-03-19 00:30:49 -05:00
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: MFCTR 9 MFSPR ;
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2005-03-13 17:55:57 -05:00
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: MTSPR 5 shift 467 xfx-form 31 insn ;
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: MTLR 8 MTSPR ;
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2005-03-19 00:30:49 -05:00
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: MTCTR 9 MTSPR ;
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2005-03-14 13:20:57 -05:00
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: LWZ d-form 32 insn ;
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: STW d-form 36 insn ;
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: STWU d-form 37 insn ;
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2005-03-17 23:29:08 -05:00
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: CMPI d-form 11 insn ;
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2005-03-19 21:23:21 -05:00
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: LOAD32 >r w>h/h r> tuck LIS dup rot ORI ;
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2005-03-17 23:29:08 -05:00
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: LOAD ( n r -- )
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#! PowerPC cannot load a 32 bit literal in one instruction.
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2005-03-19 21:23:21 -05:00
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>r dup dup HEX: ffff bitand = [ r> LI ] [ r> LOAD32 ] ifte ;
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