add intrinsics for v<=, v<, v=, v>, v>=, vunordered?
Joe Groff
parent
74f15cfe8c
commit
04bb03bb61
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@ -177,7 +177,12 @@ IN: compiler.cfg.intrinsics
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{ math.vectors.simd.intrinsics:(simd-vor) [ [ ^^or-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vxor) [ [ ^^xor-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vnot) [ [ ^^not-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-v<=) [ [ cc<= ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-v<) [ [ cc< ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-v=) [ [ cc= ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-v>) [ [ cc> ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-v>=) [ [ cc>= ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vunordered?) [ [ cc/<>= ^^compare-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vany?) [ [ vcc-any ^^test-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vall?) [ [ vcc-all ^^test-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vnone?) [ [ vcc-none ^^test-vector ] emit-unary-vector-op ] }
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@ -31,7 +31,12 @@ IN: compiler.tree.propagation.simd
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(simd-hlshift)
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(simd-hrshift)
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(simd-vshuffle)
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(simd-v<=)
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(simd-v<)
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(simd-v=)
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(simd-v>)
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(simd-v>=)
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(simd-vunordered?)
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(simd-with)
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(simd-gather-2)
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(simd-gather-4)
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@ -256,7 +256,7 @@ HOOK: %fill-vector-reps cpu ( -- reps )
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HOOK: %gather-vector-2-reps cpu ( -- reps )
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HOOK: %gather-vector-4-reps cpu ( -- reps )
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HOOK: %shuffle-vector-reps cpu ( -- reps )
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HOOK: %compare-vector-reps cpu ( -- reps )
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HOOK: %compare-vector-reps cpu ( cc -- reps )
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HOOK: %test-vector-reps cpu ( -- reps )
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HOOK: %add-vector-reps cpu ( -- reps )
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HOOK: %saturated-add-vector-reps cpu ( -- reps )
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@ -262,7 +262,7 @@ M: ppc %fill-vector-reps { } ;
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M: ppc %gather-vector-2-reps { } ;
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M: ppc %gather-vector-4-reps { } ;
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M: ppc %shuffle-vector-reps { } ;
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M: ppc %compare-vector-reps { } ;
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M: ppc %compare-vector-reps drop { } ;
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M: ppc %test-vector-reps { } ;
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M: ppc %add-vector-reps { } ;
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M: ppc %saturated-add-vector-reps { } ;
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@ -770,12 +770,30 @@ M: x86 %compare-vector ( dst src1 src2 temp rep cc -- )
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[ %compare-float-vector ]
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[ %compare-int-vector ] if ;
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M: x86 %compare-vector-reps
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: %compare-vector-eq-reps ( -- reps )
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{
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{ sse? { float-4-rep } }
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{ sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep } }
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{ sse4.1? { longlong-2-rep ulonglong-2-rep } }
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} available-reps ;
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: %compare-vector-unord-reps ( -- reps )
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{
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{ sse? { float-4-rep } }
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{ sse2? { double-2-rep } }
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} available-reps ;
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: %compare-vector-ord-reps ( -- reps )
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{
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{ sse? { float-4-rep } }
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{ sse2? { double-2-rep char-16-rep short-8-rep int-4-rep } }
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{ sse4.1? { longlong-2-rep } }
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} available-reps ;
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M: x86 %compare-vector-reps
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{
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{ [ dup { cc= cc/= } memq? ] [ drop %compare-vector-eq-reps ] }
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{ [ dup { cc<>= cc/<>= } memq? ] [ drop %compare-vector-unord-reps ] }
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[ drop %compare-vector-ord-reps ]
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} cond ;
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:: %test-vector-mask ( dst temp mask vcc -- )
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vcc {
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@ -1,9 +1,9 @@
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! Copyright (C) 2009 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: alien alien.c-types alien.data assocs combinators
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cpu.architecture fry generalizations kernel libc macros math
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sequences effects accessors namespaces lexer parser vocabs.parser
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words arrays math.vectors ;
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cpu.architecture compiler.cfg.comparisons fry generalizations
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kernel libc macros math sequences effects accessors namespaces
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lexer parser vocabs.parser words arrays math.vectors ;
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IN: math.vectors.simd.intrinsics
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ERROR: bad-simd-call ;
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@ -55,7 +55,12 @@ SIMD-OP: vrshift
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SIMD-OP: hlshift
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SIMD-OP: hrshift
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SIMD-OP: vshuffle
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SIMD-OP: v<=
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SIMD-OP: v<
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SIMD-OP: v=
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SIMD-OP: v>
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SIMD-OP: v>=
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SIMD-OP: vunordered?
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SIMD-OP: vany?
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SIMD-OP: vall?
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SIMD-OP: vnone?
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@ -113,39 +118,44 @@ GENERIC# supported-simd-op? 1 ( rep intrinsic -- ? )
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M: vector-rep supported-simd-op?
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{
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{ \ (simd-v+) [ %add-vector-reps ] }
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{ \ (simd-vs+) [ %saturated-add-vector-reps ] }
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{ \ (simd-v+-) [ %add-sub-vector-reps ] }
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{ \ (simd-v-) [ %sub-vector-reps ] }
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{ \ (simd-vs-) [ %saturated-sub-vector-reps ] }
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{ \ (simd-v*) [ %mul-vector-reps ] }
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{ \ (simd-vs*) [ %saturated-mul-vector-reps ] }
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{ \ (simd-v/) [ %div-vector-reps ] }
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{ \ (simd-vmin) [ %min-vector-reps ] }
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{ \ (simd-vmax) [ %max-vector-reps ] }
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{ \ (simd-v.) [ %dot-vector-reps ] }
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{ \ (simd-vsqrt) [ %sqrt-vector-reps ] }
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{ \ (simd-sum) [ %horizontal-add-vector-reps ] }
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{ \ (simd-vabs) [ %abs-vector-reps ] }
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{ \ (simd-vbitand) [ %and-vector-reps ] }
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{ \ (simd-vbitandn) [ %andn-vector-reps ] }
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{ \ (simd-vbitor) [ %or-vector-reps ] }
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{ \ (simd-vbitxor) [ %xor-vector-reps ] }
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{ \ (simd-vbitnot) [ %not-vector-reps ] }
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{ \ (simd-vand) [ %and-vector-reps ] }
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{ \ (simd-vandn) [ %andn-vector-reps ] }
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{ \ (simd-vor) [ %or-vector-reps ] }
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{ \ (simd-vxor) [ %xor-vector-reps ] }
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{ \ (simd-vnot) [ %not-vector-reps ] }
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{ \ (simd-vlshift) [ %shl-vector-reps ] }
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{ \ (simd-vrshift) [ %shr-vector-reps ] }
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{ \ (simd-hlshift) [ %horizontal-shl-vector-reps ] }
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{ \ (simd-hrshift) [ %horizontal-shr-vector-reps ] }
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{ \ (simd-vshuffle) [ %shuffle-vector-reps ] }
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{ \ (simd-v=) [ %compare-vector-reps ] }
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{ \ (simd-gather-2) [ %gather-vector-2-reps ] }
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{ \ (simd-gather-4) [ %gather-vector-4-reps ] }
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{ \ (simd-vany?) [ %test-vector-reps ] }
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{ \ (simd-vall?) [ %test-vector-reps ] }
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{ \ (simd-vnone?) [ %test-vector-reps ] }
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{ \ (simd-v+) [ %add-vector-reps ] }
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{ \ (simd-vs+) [ %saturated-add-vector-reps ] }
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{ \ (simd-v+-) [ %add-sub-vector-reps ] }
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{ \ (simd-v-) [ %sub-vector-reps ] }
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{ \ (simd-vs-) [ %saturated-sub-vector-reps ] }
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{ \ (simd-v*) [ %mul-vector-reps ] }
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{ \ (simd-vs*) [ %saturated-mul-vector-reps ] }
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{ \ (simd-v/) [ %div-vector-reps ] }
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{ \ (simd-vmin) [ %min-vector-reps ] }
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{ \ (simd-vmax) [ %max-vector-reps ] }
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{ \ (simd-v.) [ %dot-vector-reps ] }
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{ \ (simd-vsqrt) [ %sqrt-vector-reps ] }
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{ \ (simd-sum) [ %horizontal-add-vector-reps ] }
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{ \ (simd-vabs) [ %abs-vector-reps ] }
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{ \ (simd-vbitand) [ %and-vector-reps ] }
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{ \ (simd-vbitandn) [ %andn-vector-reps ] }
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{ \ (simd-vbitor) [ %or-vector-reps ] }
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{ \ (simd-vbitxor) [ %xor-vector-reps ] }
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{ \ (simd-vbitnot) [ %not-vector-reps ] }
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{ \ (simd-vand) [ %and-vector-reps ] }
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{ \ (simd-vandn) [ %andn-vector-reps ] }
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{ \ (simd-vor) [ %or-vector-reps ] }
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{ \ (simd-vxor) [ %xor-vector-reps ] }
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{ \ (simd-vnot) [ %not-vector-reps ] }
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{ \ (simd-vlshift) [ %shl-vector-reps ] }
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{ \ (simd-vrshift) [ %shr-vector-reps ] }
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{ \ (simd-hlshift) [ %horizontal-shl-vector-reps ] }
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{ \ (simd-hrshift) [ %horizontal-shr-vector-reps ] }
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{ \ (simd-vshuffle) [ %shuffle-vector-reps ] }
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{ \ (simd-v<=) [ cc<= %compare-vector-reps ] }
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{ \ (simd-v<) [ cc< %compare-vector-reps ] }
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{ \ (simd-v=) [ cc= %compare-vector-reps ] }
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{ \ (simd-v>) [ cc> %compare-vector-reps ] }
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{ \ (simd-v>=) [ cc>= %compare-vector-reps ] }
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{ \ (simd-vunordered?) [ cc/<>= %compare-vector-reps ] }
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{ \ (simd-gather-2) [ %gather-vector-2-reps ] }
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{ \ (simd-gather-4) [ %gather-vector-4-reps ] }
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{ \ (simd-vany?) [ %test-vector-reps ] }
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{ \ (simd-vall?) [ %test-vector-reps ] }
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{ \ (simd-vnone?) [ %test-vector-reps ] }
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} case member? ;
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@ -98,7 +98,12 @@ H{
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{ hrshift { +vector+ +literal+ -> +vector+ } }
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{ vshuffle { +vector+ +literal+ -> +vector+ } }
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{ vbroadcast { +vector+ +literal+ -> +vector+ } }
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{ v<= { +vector+ +vector+ -> +vector+ } }
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{ v< { +vector+ +vector+ -> +vector+ } }
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{ v= { +vector+ +vector+ -> +vector+ } }
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{ v> { +vector+ +vector+ -> +vector+ } }
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{ v>= { +vector+ +vector+ -> +vector+ } }
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{ vunordered? { +vector+ +vector+ -> +vector+ } }
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{ vany? { +vector+ -> +scalar+ } }
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{ vall? { +vector+ -> +scalar+ } }
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{ vnone? { +vector+ -> +scalar+ } }
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