compiler.cfg: Fixing test failures
parent
7068de6cd3
commit
13c3fdcb5c
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@ -120,12 +120,12 @@ M: binary-expr simplify*
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M: expr simplify* drop f ;
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M: expr simplify* drop f ;
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: simplify ( expr -- simplified? vn )
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: simplify ( expr -- vn )
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dup simplify* {
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dup simplify* {
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{ [ dup not ] [ drop expr>vn f ] }
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{ [ dup not ] [ drop expr>vn ] }
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{ [ dup expr? ] [ expr>vn nip t ] }
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{ [ dup expr? ] [ expr>vn nip ] }
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{ [ dup integer? ] [ nip t ] }
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{ [ dup integer? ] [ nip ] }
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} cond swap ;
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} cond ;
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: number-values ( insn -- simplified? )
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: number-values ( insn -- )
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[ >expr simplify ] [ dst>> set-vn ] bi ;
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[ >expr simplify ] [ dst>> ] bi set-vn ;
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@ -35,9 +35,9 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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[
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[
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{
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{
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T{ ##load-reference f V int-regs 0 0.0 }
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T{ ##load-reference f V int-regs 0 0.0 }
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T{ ##load-reference f V int-regs 1 0.0 }
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T{ ##copy f V int-regs 1 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 0 D 1 }
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T{ ##replace f V int-regs 1 D 1 }
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}
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}
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] [
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] [
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{
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{
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@ -51,9 +51,9 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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[
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[
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{
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{
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T{ ##load-reference f V int-regs 0 t }
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T{ ##load-reference f V int-regs 0 t }
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T{ ##load-reference f V int-regs 1 t }
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T{ ##copy f V int-regs 1 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 0 D 1 }
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T{ ##replace f V int-regs 1 D 1 }
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}
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}
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] [
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] [
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{
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{
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@ -64,29 +64,14 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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} value-numbering-step
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} value-numbering-step
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] unit-test
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] unit-test
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! Copy propagation
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[
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{
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T{ ##peek f V int-regs 45 D 1 }
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T{ ##copy f V int-regs 48 V int-regs 45 }
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T{ ##compare-imm-branch f V int-regs 45 7 cc/= }
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}
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] [
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{
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T{ ##peek f V int-regs 45 D 1 }
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T{ ##copy f V int-regs 48 V int-regs 45 }
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T{ ##compare-imm-branch f V int-regs 48 7 cc/= }
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} value-numbering-step
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] unit-test
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! Compare propagation
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! Compare propagation
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[
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[
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{
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{
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T{ ##load-reference f V int-regs 1 + }
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T{ ##load-reference f V int-regs 1 + }
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T{ ##peek f V int-regs 2 D 0 }
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T{ ##peek f V int-regs 2 D 0 }
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T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc> }
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T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc> }
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T{ ##compare f V int-regs 6 V int-regs 2 V int-regs 1 cc> }
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T{ ##copy f V int-regs 6 V int-regs 4 }
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T{ ##replace f V int-regs 4 D 0 }
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T{ ##replace f V int-regs 6 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -612,8 +597,8 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##add-imm f V int-regs 3 V int-regs 0 0 }
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T{ ##copy f V int-regs 3 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 3 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -630,8 +615,8 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##add-imm f V int-regs 3 V int-regs 0 0 }
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T{ ##copy f V int-regs 3 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 3 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -648,8 +633,8 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##or-imm f V int-regs 3 V int-regs 0 0 }
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T{ ##copy f V int-regs 3 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 3 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -666,8 +651,8 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##load-immediate f V int-regs 2 0 }
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T{ ##xor-imm f V int-regs 3 V int-regs 0 0 }
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T{ ##copy f V int-regs 3 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 3 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -683,8 +668,8 @@ compiler.cfg assocs vectors arrays layouts namespaces ;
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{
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{
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##load-immediate f V int-regs 1 1 }
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T{ ##load-immediate f V int-regs 1 1 }
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T{ ##shl-imm f V int-regs 2 V int-regs 0 0 }
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T{ ##copy f V int-regs 2 V int-regs 0 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##replace f V int-regs 2 D 0 }
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}
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}
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] [
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] [
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{
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{
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@ -12,8 +12,9 @@ compiler.cfg.value-numbering.rewrite ;
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IN: compiler.cfg.value-numbering
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IN: compiler.cfg.value-numbering
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! Local value numbering. Predecessors must be recomputed after this
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! Local value numbering. Predecessors must be recomputed after this
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: >copy ( insn -- ##copy )
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: >copy ( insn -- insn/##copy )
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dst>> dup vreg>vn vn>vreg \ ##copy new-insn ;
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dup dst>> dup vreg>vn vn>vreg
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2dup eq? [ 2drop ] [ \ ##copy new-insn nip ] if ;
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: rewrite-loop ( insn -- insn' )
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: rewrite-loop ( insn -- insn' )
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dup rewrite [ rewrite-loop ] [ ] ?if ;
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dup rewrite [ rewrite-loop ] [ ] ?if ;
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@ -23,7 +24,7 @@ GENERIC: process-instruction ( insn -- insn' )
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M: ##flushable process-instruction
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M: ##flushable process-instruction
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dup rewrite
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dup rewrite
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[ process-instruction ]
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[ process-instruction ]
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[ dup number-values [ >copy ] when ] ?if ;
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[ dup number-values >copy ] ?if ;
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M: insn process-instruction
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M: insn process-instruction
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dup rewrite
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dup rewrite
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@ -1,42 +1,43 @@
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USING: compiler.cfg.write-barrier compiler.cfg.instructions
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USING: compiler.cfg.write-barrier compiler.cfg.instructions
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compiler.cfg.registers compiler.cfg.debugger cpu.architecture
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compiler.cfg.registers compiler.cfg.debugger cpu.architecture
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arrays tools.test vectors compiler.cfg kernel accessors ;
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arrays tools.test vectors compiler.cfg kernel accessors
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compiler.cfg.utilities ;
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IN: compiler.cfg.write-barrier.tests
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IN: compiler.cfg.write-barrier.tests
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: test-write-barrier ( insns -- insns )
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: test-write-barrier ( insns -- insns )
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write-barriers-step ;
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<simple-block> dup write-barriers-step instructions>> ;
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[
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[
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{
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V{
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T{ ##peek f V int-regs 4 D 0 f }
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T{ ##peek f V int-regs 4 D 0 f }
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T{ ##copy f V int-regs 6 V int-regs 4 f }
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T{ ##allot f V int-regs 7 24 array V int-regs 8 f }
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T{ ##allot f V int-regs 7 24 array V int-regs 8 f }
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T{ ##load-immediate f V int-regs 9 8 f }
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T{ ##load-immediate f V int-regs 9 8 f }
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T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 f }
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T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 f }
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T{ ##set-slot-imm f V int-regs 6 V int-regs 7 2 3 f }
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T{ ##set-slot-imm f V int-regs 4 V int-regs 7 2 3 f }
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T{ ##replace f V int-regs 7 D 0 f }
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T{ ##replace f V int-regs 7 D 0 f }
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T{ ##branch }
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}
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}
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] [
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] [
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{
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{
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T{ ##peek f V int-regs 4 D 0 }
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T{ ##peek f V int-regs 4 D 0 }
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T{ ##copy f V int-regs 6 V int-regs 4 }
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T{ ##allot f V int-regs 7 24 array V int-regs 8 }
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T{ ##allot f V int-regs 7 24 array V int-regs 8 }
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T{ ##load-immediate f V int-regs 9 8 }
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T{ ##load-immediate f V int-regs 9 8 }
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T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 }
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T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 }
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T{ ##write-barrier f V int-regs 7 V int-regs 10 V int-regs 11 }
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T{ ##write-barrier f V int-regs 7 V int-regs 10 V int-regs 11 }
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T{ ##set-slot-imm f V int-regs 6 V int-regs 7 2 3 }
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T{ ##set-slot-imm f V int-regs 4 V int-regs 7 2 3 }
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T{ ##write-barrier f V int-regs 7 V int-regs 12 V int-regs 13 }
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T{ ##write-barrier f V int-regs 7 V int-regs 12 V int-regs 13 }
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T{ ##replace f V int-regs 7 D 0 }
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T{ ##replace f V int-regs 7 D 0 }
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} test-write-barrier
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} test-write-barrier
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] unit-test
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] unit-test
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[
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[
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{
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V{
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T{ ##load-immediate f V int-regs 4 24 }
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T{ ##load-immediate f V int-regs 4 24 }
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T{ ##peek f V int-regs 5 D -1 }
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T{ ##peek f V int-regs 5 D -1 }
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T{ ##peek f V int-regs 6 D -2 }
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T{ ##peek f V int-regs 6 D -2 }
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T{ ##set-slot-imm f V int-regs 5 V int-regs 6 3 2 }
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T{ ##set-slot-imm f V int-regs 5 V int-regs 6 3 2 }
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T{ ##write-barrier f V int-regs 6 V int-regs 7 V int-regs 8 }
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T{ ##write-barrier f V int-regs 6 V int-regs 7 V int-regs 8 }
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T{ ##branch }
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}
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}
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] [
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] [
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{
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{
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@ -49,28 +50,23 @@ IN: compiler.cfg.write-barrier.tests
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] unit-test
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] unit-test
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[
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[
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{
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V{
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T{ ##peek f V int-regs 19 D -3 }
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T{ ##peek f V int-regs 19 D -3 }
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T{ ##peek f V int-regs 22 D -2 }
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T{ ##peek f V int-regs 22 D -2 }
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T{ ##copy f V int-regs 23 V int-regs 19 }
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T{ ##set-slot-imm f V int-regs 22 V int-regs 19 3 2 }
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T{ ##set-slot-imm f V int-regs 22 V int-regs 23 3 2 }
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T{ ##write-barrier f V int-regs 19 V int-regs 24 V int-regs 25 }
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T{ ##write-barrier f V int-regs 23 V int-regs 24 V int-regs 25 }
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T{ ##copy f V int-regs 26 V int-regs 19 }
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T{ ##peek f V int-regs 28 D -1 }
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T{ ##peek f V int-regs 28 D -1 }
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T{ ##copy f V int-regs 29 V int-regs 19 }
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T{ ##set-slot-imm f V int-regs 28 V int-regs 19 4 2 }
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T{ ##set-slot-imm f V int-regs 28 V int-regs 29 4 2 }
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T{ ##branch }
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}
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}
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] [
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] [
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{
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{
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T{ ##peek f V int-regs 19 D -3 }
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T{ ##peek f V int-regs 19 D -3 }
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T{ ##peek f V int-regs 22 D -2 }
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T{ ##peek f V int-regs 22 D -2 }
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T{ ##copy f V int-regs 23 V int-regs 19 }
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T{ ##set-slot-imm f V int-regs 22 V int-regs 19 3 2 }
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T{ ##set-slot-imm f V int-regs 22 V int-regs 23 3 2 }
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T{ ##write-barrier f V int-regs 19 V int-regs 24 V int-regs 25 }
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T{ ##write-barrier f V int-regs 23 V int-regs 24 V int-regs 25 }
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T{ ##copy f V int-regs 26 V int-regs 19 }
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T{ ##peek f V int-regs 28 D -1 }
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T{ ##peek f V int-regs 28 D -1 }
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T{ ##copy f V int-regs 29 V int-regs 19 }
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T{ ##set-slot-imm f V int-regs 28 V int-regs 19 4 2 }
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T{ ##set-slot-imm f V int-regs 28 V int-regs 29 4 2 }
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T{ ##write-barrier f V int-regs 19 V int-regs 30 V int-regs 3 }
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T{ ##write-barrier f V int-regs 29 V int-regs 30 V int-regs 3 }
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} test-write-barrier
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} test-write-barrier
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] unit-test
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] unit-test
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