Merge branch 'master' of git://factorcode.org/git/factor
U-SLAVA-DFB8FF805\Slava
commit
18fdf64931
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@ -1,16 +0,0 @@
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! Copyright (C) 2008 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: kernel words sequences lexer parser fry ;
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IN: cpu.x86.syntax
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: define-register ( name num size -- )
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[ "cpu.x86" create dup define-symbol ]
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[ dupd "register" set-word-prop ]
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[ "register-size" set-word-prop ]
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tri* ;
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: define-registers ( names size -- )
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[ dup length ] dip '[ _ define-register ] 2each ;
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: REGISTERS: ( -- )
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scan-word ";" parse-tokens swap define-registers ; parsing
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@ -1 +0,0 @@
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unportable
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@ -1,470 +0,0 @@
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! Copyright (C) 2005, 2008 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: arrays compiler.constants compiler.backend
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compiler.codegen.fixup io.binary kernel combinators
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kernel.private math namespaces make sequences words system
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layouts math.order accessors cpu.x86.syntax ;
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IN: cpu.x86
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! A postfix assembler for x86 and AMD64.
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! In 32-bit mode, { 1234 } is absolute indirect addressing.
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! In 64-bit mode, { 1234 } is RIP-relative.
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! Beware!
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! Register operands -- eg, ECX
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REGISTERS: 8 AL CL DL BL ;
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REGISTERS: 16 AX CX DX BX SP BP SI DI ;
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REGISTERS: 32 EAX ECX EDX EBX ESP EBP ESI EDI ;
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REGISTERS: 64
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RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 ;
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REGISTERS: 128
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XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
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XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ;
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TUPLE: byte value ;
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C: <byte> byte
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<PRIVATE
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#! Extended AMD64 registers (R8-R15) return true.
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GENERIC: extended? ( op -- ? )
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M: object extended? drop f ;
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PREDICATE: register < word
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"register" word-prop ;
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PREDICATE: register-8 < register
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"register-size" word-prop 8 = ;
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PREDICATE: register-16 < register
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"register-size" word-prop 16 = ;
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PREDICATE: register-32 < register
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"register-size" word-prop 32 = ;
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PREDICATE: register-64 < register
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"register-size" word-prop 64 = ;
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PREDICATE: register-128 < register
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"register-size" word-prop 128 = ;
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M: register extended? "register" word-prop 7 > ;
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! Addressing modes
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TUPLE: indirect base index scale displacement ;
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M: indirect extended? base>> extended? ;
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: canonicalize-EBP ( indirect -- indirect )
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#! { EBP } ==> { EBP 0 }
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dup base>> { EBP RBP R13 } member? [
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dup displacement>> [ 0 >>displacement ] unless
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] when ;
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: canonicalize-ESP ( indirect -- indirect )
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#! { ESP } ==> { ESP ESP }
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dup base>> { ESP RSP R12 } member? [ ESP >>index ] when ;
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: canonicalize ( indirect -- indirect )
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#! Modify the indirect to work around certain addressing mode
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#! quirks.
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canonicalize-EBP canonicalize-ESP ;
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: <indirect> ( base index scale displacement -- indirect )
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indirect boa canonicalize ;
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: reg-code ( reg -- n ) "register" word-prop 7 bitand ;
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: indirect-base* ( op -- n ) base>> EBP or reg-code ;
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: indirect-index* ( op -- n ) index>> ESP or reg-code ;
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: indirect-scale* ( op -- n ) scale>> 0 or ;
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GENERIC: sib-present? ( op -- ? )
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M: indirect sib-present?
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[ base>> { ESP RSP } member? ] [ index>> ] [ scale>> ] tri or or ;
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M: register sib-present? drop f ;
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GENERIC: r/m ( operand -- n )
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M: indirect r/m
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dup sib-present?
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[ drop ESP reg-code ] [ indirect-base* ] if ;
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M: register r/m reg-code ;
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! Immediate operands
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UNION: immediate byte integer ;
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GENERIC: fits-in-byte? ( value -- ? )
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M: byte fits-in-byte? drop t ;
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M: integer fits-in-byte? -128 127 between? ;
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GENERIC: modifier ( op -- n )
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M: indirect modifier
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dup base>> [
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displacement>> {
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{ [ dup not ] [ BIN: 00 ] }
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{ [ dup fits-in-byte? ] [ BIN: 01 ] }
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{ [ dup immediate? ] [ BIN: 10 ] }
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} cond nip
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] [
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drop BIN: 00
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] if ;
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M: register modifier drop BIN: 11 ;
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GENERIC# n, 1 ( value n -- )
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M: integer n, >le % ;
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M: byte n, >r value>> r> n, ;
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: 1, ( n -- ) 1 n, ; inline
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: 4, ( n -- ) 4 n, ; inline
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: 2, ( n -- ) 2 n, ; inline
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: cell, ( n -- ) bootstrap-cell n, ; inline
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: mod-r/m, ( reg# indirect -- )
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[ 3 shift ] [ [ modifier 6 shift ] [ r/m ] bi ] bi* bitor bitor , ;
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: sib, ( indirect -- )
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dup sib-present? [
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[ indirect-base* ]
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[ indirect-index* 3 shift ]
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[ indirect-scale* 6 shift ] tri bitor bitor ,
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] [
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drop
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] if ;
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GENERIC: displacement, ( op -- )
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M: indirect displacement,
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dup displacement>> dup [
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swap base>>
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[ dup fits-in-byte? [ , ] [ 4, ] if ] [ 4, ] if
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] [
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2drop
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] if ;
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M: register displacement, drop ;
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: addressing ( reg# indirect -- )
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[ mod-r/m, ] [ sib, ] [ displacement, ] tri ;
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! Utilities
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UNION: operand register indirect ;
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GENERIC: operand-64? ( operand -- ? )
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M: indirect operand-64?
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[ base>> ] [ index>> ] bi [ operand-64? ] either? ;
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M: register-64 operand-64? drop t ;
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M: object operand-64? drop f ;
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: rex.w? ( rex.w reg r/m -- ? )
|
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{
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{ [ dup register-128? ] [ drop operand-64? ] }
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{ [ dup not ] [ drop operand-64? ] }
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[ nip operand-64? ]
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} cond and ;
|
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|
||||
: rex.r ( m op -- n )
|
||||
extended? [ BIN: 00000100 bitor ] when ;
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: rex.b ( m op -- n )
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[ extended? [ BIN: 00000001 bitor ] when ] keep
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dup indirect? [
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index>> extended? [ BIN: 00000010 bitor ] when
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] [
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drop
|
||||
] if ;
|
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|
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: rex-prefix ( reg r/m rex.w -- )
|
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#! Compile an AMD64 REX prefix.
|
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2over rex.w? BIN: 01001000 BIN: 01000000 ?
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swap rex.r swap rex.b
|
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dup BIN: 01000000 = [ drop ] [ , ] if ;
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: 16-prefix ( reg r/m -- )
|
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[ register-16? ] either? [ HEX: 66 , ] when ;
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: prefix ( reg r/m rex.w -- ) 2over 16-prefix rex-prefix ;
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|
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: prefix-1 ( reg rex.w -- ) f swap prefix ;
|
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|
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: short-operand ( reg rex.w n -- )
|
||||
#! Some instructions encode their single operand as part of
|
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#! the opcode.
|
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>r dupd prefix-1 reg-code r> + , ;
|
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|
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: opcode, ( opcode -- ) dup array? [ % ] [ , ] if ;
|
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|
||||
: extended-opcode ( opcode -- opcode' ) OCT: 17 swap 2array ;
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: extended-opcode, ( opcode -- ) extended-opcode opcode, ;
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||||
: opcode-or ( opcode mask -- opcode' )
|
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swap dup array?
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[ unclip-last rot bitor suffix ] [ bitor ] if ;
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: 1-operand ( op reg,rex.w,opcode -- )
|
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#! The 'reg' is not really a register, but a value for the
|
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#! 'reg' field of the mod-r/m byte.
|
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first3 >r >r over r> prefix-1 r> opcode, swap addressing ;
|
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||||
: immediate-operand-size-bit ( imm dst reg,rex.w,opcode -- imm dst reg,rex.w,opcode )
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pick integer? [ first3 BIN: 1 opcode-or 3array ] when ;
|
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: immediate-1 ( imm dst reg,rex.w,opcode -- )
|
||||
immediate-operand-size-bit 1-operand 1, ;
|
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||||
: immediate-4 ( imm dst reg,rex.w,opcode -- )
|
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immediate-operand-size-bit 1-operand 4, ;
|
||||
|
||||
: immediate-fits-in-size-bit ( imm dst reg,rex.w,opcode -- imm dst reg,rex.w,opcode )
|
||||
pick integer? [ first3 BIN: 10 opcode-or 3array ] when ;
|
||||
|
||||
: immediate-1/4 ( imm dst reg,rex.w,opcode -- )
|
||||
#! If imm is a byte, compile the opcode and the byte.
|
||||
#! Otherwise, set the 8-bit operand flag in the opcode, and
|
||||
#! compile the cell. The 'reg' is not really a register, but
|
||||
#! a value for the 'reg' field of the mod-r/m byte.
|
||||
pick fits-in-byte? [
|
||||
immediate-fits-in-size-bit immediate-1
|
||||
] [
|
||||
immediate-4
|
||||
] if ;
|
||||
|
||||
: (2-operand) ( dst src op -- )
|
||||
>r 2dup t rex-prefix r> opcode,
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reg-code swap addressing ;
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||||
|
||||
: direction-bit ( dst src op -- dst' src' op' )
|
||||
pick register? [ BIN: 10 opcode-or swapd ] when ;
|
||||
|
||||
: operand-size-bit ( dst src op -- dst' src' op' )
|
||||
over register-8? [ BIN: 1 opcode-or ] unless ;
|
||||
|
||||
: 2-operand ( dst src op -- )
|
||||
#! Sets the opcode's direction bit. It is set if the
|
||||
#! destination is a direct register operand.
|
||||
2over 16-prefix
|
||||
direction-bit
|
||||
operand-size-bit
|
||||
(2-operand) ;
|
||||
|
||||
PRIVATE>
|
||||
|
||||
: [] ( reg/displacement -- indirect )
|
||||
dup integer? [ >r f f f r> ] [ f f f ] if <indirect> ;
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||||
|
||||
: [+] ( reg displacement -- indirect )
|
||||
dup integer?
|
||||
[ dup zero? [ drop f ] when >r f f r> ]
|
||||
[ f f ] if
|
||||
<indirect> ;
|
||||
|
||||
! Moving stuff
|
||||
GENERIC: PUSH ( op -- )
|
||||
M: register PUSH f HEX: 50 short-operand ;
|
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M: immediate PUSH HEX: 68 , 4, ;
|
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M: operand PUSH { BIN: 110 f HEX: ff } 1-operand ;
|
||||
|
||||
GENERIC: POP ( op -- )
|
||||
M: register POP f HEX: 58 short-operand ;
|
||||
M: operand POP { BIN: 000 f HEX: 8f } 1-operand ;
|
||||
|
||||
! MOV where the src is immediate.
|
||||
GENERIC: (MOV-I) ( src dst -- )
|
||||
M: register (MOV-I) t HEX: b8 short-operand cell, ;
|
||||
M: operand (MOV-I)
|
||||
{ BIN: 000 t HEX: c6 }
|
||||
pick byte? [ immediate-1 ] [ immediate-4 ] if ;
|
||||
|
||||
GENERIC: MOV ( dst src -- )
|
||||
M: immediate MOV swap (MOV-I) ;
|
||||
M: word MOV 0 rot (MOV-I) rc-absolute-cell rel-word ;
|
||||
M: operand MOV HEX: 88 2-operand ;
|
||||
|
||||
: LEA ( dst src -- ) swap HEX: 8d 2-operand ;
|
||||
|
||||
! Control flow
|
||||
GENERIC: JMP ( op -- )
|
||||
: (JMP) ( -- rel-class ) HEX: e9 , 0 4, rc-relative ;
|
||||
M: word JMP (JMP) rel-word ;
|
||||
M: label JMP (JMP) label-fixup ;
|
||||
M: operand JMP { BIN: 100 t HEX: ff } 1-operand ;
|
||||
|
||||
GENERIC: CALL ( op -- )
|
||||
: (CALL) ( -- rel-class ) HEX: e8 , 0 4, rc-relative ;
|
||||
M: word CALL (CALL) rel-word ;
|
||||
M: label CALL (CALL) label-fixup ;
|
||||
M: operand CALL { BIN: 010 t HEX: ff } 1-operand ;
|
||||
|
||||
GENERIC# JUMPcc 1 ( addr opcode -- )
|
||||
: (JUMPcc) ( n -- rel-class ) extended-opcode, 0 4, rc-relative ;
|
||||
M: word JUMPcc (JUMPcc) rel-word ;
|
||||
M: label JUMPcc (JUMPcc) label-fixup ;
|
||||
|
||||
: JO ( dst -- ) HEX: 80 JUMPcc ;
|
||||
: JNO ( dst -- ) HEX: 81 JUMPcc ;
|
||||
: JB ( dst -- ) HEX: 82 JUMPcc ;
|
||||
: JAE ( dst -- ) HEX: 83 JUMPcc ;
|
||||
: JE ( dst -- ) HEX: 84 JUMPcc ; ! aka JZ
|
||||
: JNE ( dst -- ) HEX: 85 JUMPcc ;
|
||||
: JBE ( dst -- ) HEX: 86 JUMPcc ;
|
||||
: JA ( dst -- ) HEX: 87 JUMPcc ;
|
||||
: JS ( dst -- ) HEX: 88 JUMPcc ;
|
||||
: JNS ( dst -- ) HEX: 89 JUMPcc ;
|
||||
: JP ( dst -- ) HEX: 8a JUMPcc ;
|
||||
: JNP ( dst -- ) HEX: 8b JUMPcc ;
|
||||
: JL ( dst -- ) HEX: 8c JUMPcc ;
|
||||
: JGE ( dst -- ) HEX: 8d JUMPcc ;
|
||||
: JLE ( dst -- ) HEX: 8e JUMPcc ;
|
||||
: JG ( dst -- ) HEX: 8f JUMPcc ;
|
||||
|
||||
: LEAVE ( -- ) HEX: c9 , ;
|
||||
: NOP ( -- ) HEX: 90 , ;
|
||||
|
||||
: RET ( n -- )
|
||||
dup zero? [ drop HEX: c3 , ] [ HEX: C2 , 2, ] if ;
|
||||
|
||||
! Arithmetic
|
||||
|
||||
GENERIC: ADD ( dst src -- )
|
||||
M: immediate ADD swap { BIN: 000 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand ADD OCT: 000 2-operand ;
|
||||
|
||||
GENERIC: OR ( dst src -- )
|
||||
M: immediate OR swap { BIN: 001 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand OR OCT: 010 2-operand ;
|
||||
|
||||
GENERIC: ADC ( dst src -- )
|
||||
M: immediate ADC swap { BIN: 010 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand ADC OCT: 020 2-operand ;
|
||||
|
||||
GENERIC: SBB ( dst src -- )
|
||||
M: immediate SBB swap { BIN: 011 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand SBB OCT: 030 2-operand ;
|
||||
|
||||
GENERIC: AND ( dst src -- )
|
||||
M: immediate AND swap { BIN: 100 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand AND OCT: 040 2-operand ;
|
||||
|
||||
GENERIC: SUB ( dst src -- )
|
||||
M: immediate SUB swap { BIN: 101 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand SUB OCT: 050 2-operand ;
|
||||
|
||||
GENERIC: XOR ( dst src -- )
|
||||
M: immediate XOR swap { BIN: 110 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand XOR OCT: 060 2-operand ;
|
||||
|
||||
GENERIC: CMP ( dst src -- )
|
||||
M: immediate CMP swap { BIN: 111 t HEX: 80 } immediate-1/4 ;
|
||||
M: operand CMP OCT: 070 2-operand ;
|
||||
|
||||
: NOT ( dst -- ) { BIN: 010 t HEX: f7 } 1-operand ;
|
||||
: NEG ( dst -- ) { BIN: 011 t HEX: f7 } 1-operand ;
|
||||
: MUL ( dst -- ) { BIN: 100 t HEX: f7 } 1-operand ;
|
||||
: IMUL ( src -- ) { BIN: 101 t HEX: f7 } 1-operand ;
|
||||
: DIV ( dst -- ) { BIN: 110 t HEX: f7 } 1-operand ;
|
||||
: IDIV ( src -- ) { BIN: 111 t HEX: f7 } 1-operand ;
|
||||
|
||||
: CDQ ( -- ) HEX: 99 , ;
|
||||
: CQO ( -- ) HEX: 48 , CDQ ;
|
||||
|
||||
: ROL ( dst n -- ) swap { BIN: 000 t HEX: c0 } immediate-1 ;
|
||||
: ROR ( dst n -- ) swap { BIN: 001 t HEX: c0 } immediate-1 ;
|
||||
: RCL ( dst n -- ) swap { BIN: 010 t HEX: c0 } immediate-1 ;
|
||||
: RCR ( dst n -- ) swap { BIN: 011 t HEX: c0 } immediate-1 ;
|
||||
: SHL ( dst n -- ) swap { BIN: 100 t HEX: c0 } immediate-1 ;
|
||||
: SHR ( dst n -- ) swap { BIN: 101 t HEX: c0 } immediate-1 ;
|
||||
: SAR ( dst n -- ) swap { BIN: 111 t HEX: c0 } immediate-1 ;
|
||||
|
||||
GENERIC: IMUL2 ( dst src -- )
|
||||
M: immediate IMUL2 swap dup reg-code t HEX: 68 3array immediate-1/4 ;
|
||||
M: operand IMUL2 OCT: 257 extended-opcode (2-operand) ;
|
||||
|
||||
: MOVSX ( dst src -- )
|
||||
dup register-32? OCT: 143 OCT: 276 extended-opcode ?
|
||||
over register-16? [ BIN: 1 opcode-or ] when
|
||||
swapd
|
||||
(2-operand) ;
|
||||
|
||||
! Conditional move
|
||||
: MOVcc ( dst src cc -- ) extended-opcode swapd (2-operand) ;
|
||||
|
||||
: CMOVO ( dst src -- ) HEX: 40 MOVcc ;
|
||||
: CMOVNO ( dst src -- ) HEX: 41 MOVcc ;
|
||||
: CMOVB ( dst src -- ) HEX: 42 MOVcc ;
|
||||
: CMOVAE ( dst src -- ) HEX: 43 MOVcc ;
|
||||
: CMOVE ( dst src -- ) HEX: 44 MOVcc ; ! aka CMOVZ
|
||||
: CMOVNE ( dst src -- ) HEX: 45 MOVcc ;
|
||||
: CMOVBE ( dst src -- ) HEX: 46 MOVcc ;
|
||||
: CMOVA ( dst src -- ) HEX: 47 MOVcc ;
|
||||
: CMOVS ( dst src -- ) HEX: 48 MOVcc ;
|
||||
: CMOVNS ( dst src -- ) HEX: 49 MOVcc ;
|
||||
: CMOVP ( dst src -- ) HEX: 4a MOVcc ;
|
||||
: CMOVNP ( dst src -- ) HEX: 4b MOVcc ;
|
||||
: CMOVL ( dst src -- ) HEX: 4c MOVcc ;
|
||||
: CMOVGE ( dst src -- ) HEX: 4d MOVcc ;
|
||||
: CMOVLE ( dst src -- ) HEX: 4e MOVcc ;
|
||||
: CMOVG ( dst src -- ) HEX: 4f MOVcc ;
|
||||
|
||||
! CPU Identification
|
||||
|
||||
: CPUID ( -- ) HEX: a2 extended-opcode, ;
|
||||
|
||||
! x87 Floating Point Unit
|
||||
|
||||
: FSTPS ( operand -- ) { BIN: 011 f HEX: d9 } 1-operand ;
|
||||
: FSTPL ( operand -- ) { BIN: 011 f HEX: dd } 1-operand ;
|
||||
|
||||
: FLDS ( operand -- ) { BIN: 000 f HEX: d9 } 1-operand ;
|
||||
: FLDL ( operand -- ) { BIN: 000 f HEX: dd } 1-operand ;
|
||||
|
||||
! SSE multimedia instructions
|
||||
|
||||
<PRIVATE
|
||||
|
||||
: direction-bit-sse ( dst src op1 -- dst' src' op1' )
|
||||
pick register-128? [ swapd ] [ BIN: 1 bitor ] if ;
|
||||
|
||||
: 2-operand-sse ( dst src op1 op2 -- )
|
||||
, direction-bit-sse extended-opcode (2-operand) ;
|
||||
|
||||
: 2-operand-int/sse ( dst src op1 op2 -- )
|
||||
, swapd extended-opcode (2-operand) ;
|
||||
|
||||
PRIVATE>
|
||||
|
||||
: MOVSS ( dest src -- ) HEX: 10 HEX: f3 2-operand-sse ;
|
||||
: MOVSD ( dest src -- ) HEX: 10 HEX: f2 2-operand-sse ;
|
||||
: ADDSD ( dest src -- ) HEX: 58 HEX: f2 2-operand-sse ;
|
||||
: MULSD ( dest src -- ) HEX: 59 HEX: f2 2-operand-sse ;
|
||||
: SUBSD ( dest src -- ) HEX: 5c HEX: f2 2-operand-sse ;
|
||||
: DIVSD ( dest src -- ) HEX: 5e HEX: f2 2-operand-sse ;
|
||||
: SQRTSD ( dest src -- ) HEX: 51 HEX: f2 2-operand-sse ;
|
||||
: UCOMISD ( dest src -- ) HEX: 2e HEX: 66 2-operand-sse ;
|
||||
: COMISD ( dest src -- ) HEX: 2f HEX: 66 2-operand-sse ;
|
||||
|
||||
: CVTSS2SD ( dest src -- ) HEX: 5a HEX: f3 2-operand-sse ;
|
||||
: CVTSD2SS ( dest src -- ) HEX: 5a HEX: f2 2-operand-sse ;
|
||||
|
||||
: CVTSI2SD ( dest src -- ) HEX: 2a HEX: f2 2-operand-int/sse ;
|
||||
: CVTSD2SI ( dest src -- ) HEX: 2d HEX: f2 2-operand-int/sse ;
|
||||
: CVTTSD2SI ( dest src -- ) HEX: 2c HEX: f2 2-operand-int/sse ;
|
||||
Loading…
Reference in New Issue