cpu.ppc.bootstrap: updates
parent
c802e82b97
commit
25886ff453
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@ -21,43 +21,48 @@ CONSTANT: rs-reg 14
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: xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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11 6 profile-count-offset LWZ
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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11 3 profile-count-offset LWZ
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11 11 1 tag-fixnum ADDI
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11 6 profile-count-offset STW
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11 6 word-code-offset LWZ
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11 3 profile-count-offset STW
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11 3 word-code-offset LWZ
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11 11 compiled-header-size ADDI
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11 MTCTR
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BCTR
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] jit-profiling jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-this jit-rel
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-this jit-rel
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0 MFLR
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1 1 stack-frame SUBI
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6 1 xt-save STW
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stack-frame 6 LI
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6 1 next-save STW
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3 1 xt-save STW
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stack-frame 3 LI
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3 1 next-save STW
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0 1 lr-save stack-frame + STW
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] jit-prolog jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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6 ds-reg 4 STWU
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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3 ds-reg 4 STWU
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] jit-push-immediate jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-stack-chain jit-rel
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7 6 0 LWZ
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1 7 0 STW
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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6 MTCTR
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-stack-chain jit-rel
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4 3 0 LWZ
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1 4 0 STW
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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3 MTCTR
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BCTR
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] jit-primitive jit-define
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[ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define
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[ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-word-jump jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-here jit-rel
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0 B rc-relative-ppc-3 rt-xt-pic-tail jit-rel
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] jit-word-jump jit-define
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[ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-word-special jit-define
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[
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3 ds-reg 0 LWZ
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@ -152,6 +157,9 @@ CONSTANT: rs-reg 14
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! ! ! Polymorphic inline caches
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! Don't touch r6 here; it's used to pass the tail call site
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! address for tail PICs
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! Load a value from a stack position
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[
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4 ds-reg 0 LWZ rc-absolute-ppc-2 rt-untagged jit-rel
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@ -225,7 +233,7 @@ CONSTANT: rs-reg 14
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! if(get(cache) == class)
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6 3 0 LWZ
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6 0 4 CMP
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5 BNE
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10 BNE
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! megamorphic_cache_hits++
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0 4 LOAD32 rc-absolute-ppc-2/2 rt-megamorphic-cache-hits jit-rel
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5 4 0 LWZ
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