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x86 backend work

db4
Slava Pestov 2008-01-12 18:46:22 -05:00
parent 50e6aca633
commit 2d6d22175e
2 changed files with 10 additions and 8 deletions
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3
core/cpu/x86/64/bootstrap.factor
View File

@ -8,10 +8,9 @@ IN: bootstrap.x86
: arg0 RDI ; : arg0 RDI ;
: arg1 RSI ; : arg1 RSI ;
: temp-reg RBX ;
: stack-reg RSP ; : stack-reg RSP ;
: ds-reg R14 ; : ds-reg R14 ;
: scan-reg RBX ;
: xt-reg RCX ;
: fixnum>slot@ ; : fixnum>slot@ ;
"resource:core/cpu/x86/bootstrap.factor" run-file "resource:core/cpu/x86/bootstrap.factor" run-file

15
core/cpu/x86/bootstrap.factor
View File

@ -13,7 +13,8 @@ big-endian off
[ [
! Load word ! Load word
temp-reg 0 [] MOV temp-reg 0 MOV
temp-reg dup [] MOV
! Bump profiling counter ! Bump profiling counter
temp-reg profile-count-offset [+] 1 tag-fixnum ADD temp-reg profile-count-offset [+] 1 tag-fixnum ADD
! Load word->code ! Load word->code
@ -22,7 +23,7 @@ big-endian off
temp-reg compiled-header-size ADD temp-reg compiled-header-size ADD
! Jump to XT ! Jump to XT
temp-reg JMP temp-reg JMP
] rc-absolute-cell rt-literal 2 jit-profiling jit-define ] rc-absolute-cell rt-literal 1 jit-profiling jit-define
[ [
stack-frame-size PUSH ! save stack frame size stack-frame-size PUSH ! save stack frame size
@ -31,10 +32,11 @@ big-endian off
] rc-absolute-cell rt-label 6 jit-prolog jit-define ] rc-absolute-cell rt-label 6 jit-prolog jit-define
[ [
arg0 0 [] MOV ! load literal arg0 0 MOV ! load literal
arg0 dup [] MOV
ds-reg bootstrap-cell ADD ! increment datastack pointer ds-reg bootstrap-cell ADD ! increment datastack pointer
ds-reg [] arg0 MOV ! store literal on datastack ds-reg [] arg0 MOV ! store literal on datastack
] rc-absolute-cell rt-literal 2 jit-push-literal jit-define ] rc-absolute-cell rt-literal 1 jit-push-literal jit-define
[ [
arg1 stack-reg MOV ! pass callstack pointer as arg 2 arg1 stack-reg MOV ! pass callstack pointer as arg 2
@ -60,14 +62,15 @@ big-endian off
] rc-absolute-cell rt-literal 1 jit-if-jump jit-define ] rc-absolute-cell rt-literal 1 jit-if-jump jit-define
[ [
arg1 0 [] MOV ! load dispatch table arg1 0 MOV ! load dispatch table
arg1 dup [] MOV
arg0 ds-reg [] MOV ! load index arg0 ds-reg [] MOV ! load index
fixnum>slot@ ! turn it into an array offset fixnum>slot@ ! turn it into an array offset
ds-reg bootstrap-cell SUB ! pop index ds-reg bootstrap-cell SUB ! pop index
arg0 arg1 ADD ! compute quotation location arg0 arg1 ADD ! compute quotation location
arg0 arg0 array-start [+] MOV ! load quotation arg0 arg0 array-start [+] MOV ! load quotation
arg0 quot-xt@ [+] JMP ! execute branch arg0 quot-xt@ [+] JMP ! execute branch
] rc-absolute-cell rt-literal 2 jit-dispatch jit-define ] rc-absolute-cell rt-literal 1 jit-dispatch jit-define
[ [
stack-reg stack-frame-size bootstrap-cell - ADD ! unwind stack frame stack-reg stack-frame-size bootstrap-cell - ADD ! unwind stack frame