Merge branch 'master' of git://factorcode.org/git/factor
Joe Groff
commit
2ec754e77f
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@ -21,43 +21,48 @@ CONSTANT: rs-reg 14
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: xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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11 6 profile-count-offset LWZ
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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11 3 profile-count-offset LWZ
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11 11 1 tag-fixnum ADDI
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11 6 profile-count-offset STW
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11 6 word-code-offset LWZ
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11 3 profile-count-offset STW
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11 3 word-code-offset LWZ
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11 11 compiled-header-size ADDI
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11 MTCTR
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BCTR
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] jit-profiling jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-this jit-rel
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-this jit-rel
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0 MFLR
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1 1 stack-frame SUBI
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6 1 xt-save STW
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stack-frame 6 LI
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6 1 next-save STW
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3 1 xt-save STW
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stack-frame 3 LI
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3 1 next-save STW
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0 1 lr-save stack-frame + STW
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] jit-prolog jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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6 ds-reg 4 STWU
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-immediate jit-rel
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3 ds-reg 4 STWU
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] jit-push-immediate jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-stack-chain jit-rel
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7 6 0 LWZ
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1 7 0 STW
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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6 MTCTR
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-stack-chain jit-rel
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4 3 0 LWZ
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1 4 0 STW
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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3 MTCTR
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BCTR
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] jit-primitive jit-define
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[ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define
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[ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-word-jump jit-define
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[
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0 6 LOAD32 rc-absolute-ppc-2/2 rt-here jit-rel
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0 B rc-relative-ppc-3 rt-xt-pic-tail jit-rel
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] jit-word-jump jit-define
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[ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-word-special jit-define
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[
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3 ds-reg 0 LWZ
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@ -152,6 +157,9 @@ CONSTANT: rs-reg 14
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! ! ! Polymorphic inline caches
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! Don't touch r6 here; it's used to pass the tail call site
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! address for tail PICs
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! Load a value from a stack position
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[
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4 ds-reg 0 LWZ rc-absolute-ppc-2 rt-untagged jit-rel
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@ -225,7 +233,7 @@ CONSTANT: rs-reg 14
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! if(get(cache) == class)
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6 3 0 LWZ
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6 0 4 CMP
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5 BNE
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10 BNE
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! megamorphic_cache_hits++
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0 4 LOAD32 rc-absolute-ppc-2/2 rt-megamorphic-cache-hits jit-rel
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5 4 0 LWZ
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@ -3,9 +3,10 @@
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USING: accessors assocs sequences kernel combinators make math
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math.order math.ranges system namespaces locals layouts words
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alien alien.c-types literals cpu.architecture cpu.ppc.assembler
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literals compiler.cfg.registers compiler.cfg.instructions
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compiler.constants compiler.codegen compiler.codegen.fixup
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compiler.cfg.intrinsics compiler.cfg.stack-frame ;
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cpu.ppc.assembler.backend literals compiler.cfg.registers
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compiler.cfg.instructions compiler.constants compiler.codegen
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compiler.codegen.fixup compiler.cfg.intrinsics
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compiler.cfg.stack-frame ;
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IN: cpu.ppc
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! PowerPC register assignments:
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@ -116,7 +117,7 @@ M: ppc stack-frame-size ( stack-frame -- i )
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M: ppc %call ( word -- ) 0 BL rc-relative-ppc-3 rel-word-pic ;
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M: ppc %jump ( word -- )
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0 3 LOAD32 rc-absolute-ppc-2/2 rel-here
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0 6 LOAD32 8 rc-absolute-ppc-2/2 rel-here
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0 B rc-relative-ppc-3 rel-word-pic-tail ;
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M: ppc %jump-label ( label -- ) B ;
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@ -130,7 +131,7 @@ M:: ppc %dispatch ( src temp offset -- )
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BCTR ;
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M: ppc %dispatch-label ( word -- )
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0 , rc-absolute-cell rel-word ;
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B{ 0 0 0 0 } % rc-absolute-cell rel-word ;
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:: (%slot) ( obj slot tag temp -- reg offset )
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temp slot obj ADD
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@ -233,7 +233,7 @@ big-endian off
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temp0 temp2 ADD
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! if(get(cache) == class)
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temp0 [] temp1 CMP
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bootstrap-cell 4 = 14 18 ? JNE ! Yuck!
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bootstrap-cell 4 = 14 22 ? JNE ! Yuck!
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! megamorphic_cache_hits++
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temp1 0 MOV rc-absolute-cell rt-megamorphic-cache-hits jit-rel
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temp1 [] 1 ADD
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@ -236,8 +236,10 @@ DEF(void,flush_icache,(void *start, int len)):
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blr
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DEF(void,primitive_inline_cache_miss,(void)):
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mflr r3
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mflr r6
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DEF(void,primitive_inline_cache_miss_tail,(void)):
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PROLOGUE
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mr r3,r6
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bl MANGLE(inline_cache_miss)
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EPILOGUE
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mtctr r3
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@ -7,11 +7,22 @@ namespace factor
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register cell ds asm("r13");
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register cell rs asm("r14");
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/* In the instruction sequence:
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LOAD32 r3,...
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B blah
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the offset from the immediate operand to LOAD32 to the instruction after
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the branch is two instructions. */
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static const fixnum xt_tail_pic_offset = 4 * 2;
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inline static void check_call_site(cell return_address)
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{
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#ifdef FACTOR_DEBUG
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cell insn = *(cell *)return_address;
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assert((insn & 0x3) == 0x1);
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/* Check that absolute bit is 0 */
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assert((insn & 0x2) == 0x0);
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/* Check that instruction is branch */
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assert((insn >> 26) == 0x12);
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#endif
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}
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@ -21,8 +32,8 @@ inline static void check_call_site(cell return_address)
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inline static void *get_call_target(cell return_address)
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{
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return_address -= sizeof(cell);
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check_call_site(return_address);
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cell insn = *(cell *)return_address;
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cell unsigned_addr = (insn & B_MASK);
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fixnum signed_addr = (fixnum)(unsigned_addr << 6) >> 6;
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@ -32,19 +43,25 @@ inline static void *get_call_target(cell return_address)
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inline static void set_call_target(cell return_address, void *target)
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{
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return_address -= sizeof(cell);
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#ifdef FACTOR_DEBUG
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assert((return_address & ~B_MASK) == 0);
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check_call_site(return_address);
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#endif
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cell insn = *(cell *)return_address;
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insn = ((insn & ~B_MASK) | (((cell)target - return_address) & B_MASK));
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fixnum relative_address = ((cell)target - return_address);
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insn = ((insn & ~B_MASK) | (relative_address & B_MASK));
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*(cell *)return_address = insn;
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/* Flush the cache line containing the call we just patched */
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__asm__ __volatile__ ("icbi 0, %0\n" "sync\n"::"r" (return_address):);
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}
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inline static bool tail_call_site_p(cell return_address)
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{
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return_address -= sizeof(cell);
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cell insn = *(cell *)return_address;
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return (insn & 0x1) == 0;
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}
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/* Defined in assembly */
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VM_ASM_API void c_to_factor(cell quot);
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VM_ASM_API void throw_impl(cell quot, stack_frame *rewind);
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