add intrinsic for vnot/vbitnot

basis/compiler/cfg/instructions/instructions.factor

@@ -261,6 +261,10 @@ PURE-INSN: ##zero-vector
 def: dst
 literal: rep ;
 
+PURE-INSN: ##fill-vector
+def: dst
+literal: rep ;
+
 PURE-INSN: ##gather-vector-2
 def: dst
 use: src1/scalar-rep src2/scalar-rep
@@ -403,6 +407,11 @@ def: dst
 use: src1 src2
 literal: rep ;
 
+PURE-INSN: ##not-vector
+def: dst
+use: src
+literal: rep ;
+
 PURE-INSN: ##shl-vector
 def: dst
 use: src1 src2/int-scalar-rep
@@ -765,6 +774,7 @@ UNION: kill-vreg-insn
 UNION: def-is-use-insn
 ##box-alien
 ##box-displaced-alien
+##not-vector
 ##string-nth
 ##unbox-any-c-ptr ;
 

basis/compiler/cfg/intrinsics/intrinsics.factor

@@ -171,10 +171,12 @@ IN: compiler.cfg.intrinsics
         { math.vectors.simd.intrinsics:(simd-vbitandn) [ [ ^^andn-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vbitor) [ [ ^^or-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vbitxor) [ [ ^^xor-vector ] emit-binary-vector-op ] }
+        { math.vectors.simd.intrinsics:(simd-vbitnot) [ [ ^^not-vector ] emit-unary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vand) [ [ ^^and-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vandn) [ [ ^^andn-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vor) [ [ ^^or-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vxor) [ [ ^^xor-vector ] emit-binary-vector-op ] }
+        { math.vectors.simd.intrinsics:(simd-vnot) [ [ ^^not-vector ] emit-unary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-v=) [ [ cc= ^^compare-vector ] emit-binary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vany?) [ [ vcc-any ^^test-vector ] emit-unary-vector-op ] }
         { math.vectors.simd.intrinsics:(simd-vall?) [ [ vcc-all ^^test-vector ] emit-unary-vector-op ] }

basis/compiler/codegen/codegen.factor

@@ -186,6 +186,7 @@ CODEGEN: ##and-vector %and-vector
 CODEGEN: ##andn-vector %andn-vector
 CODEGEN: ##or-vector %or-vector
 CODEGEN: ##xor-vector %xor-vector
+CODEGEN: ##not-vector %not-vector
 CODEGEN: ##shl-vector %shl-vector
 CODEGEN: ##shr-vector %shr-vector
 CODEGEN: ##integer>scalar %integer>scalar

basis/compiler/tree/propagation/simd/simd.factor

@@ -20,10 +20,12 @@ IN: compiler.tree.propagation.simd
     (simd-vbitandn)
     (simd-vbitor)
     (simd-vbitxor)
+    (simd-vbitnot)
     (simd-vand)
     (simd-vandn)
     (simd-vor)
     (simd-vxor)
+    (simd-vnot)
     (simd-vlshift)
     (simd-vrshift)
     (simd-hlshift)

basis/cpu/architecture/architecture.factor

@@ -214,6 +214,7 @@ HOOK: %integer>float cpu ( dst src -- )
 HOOK: %float>integer cpu ( dst src -- )
 
 HOOK: %zero-vector cpu ( dst rep -- )
+HOOK: %fill-vector cpu ( dst rep -- )
 HOOK: %gather-vector-2 cpu ( dst src1 src2 rep -- )
 HOOK: %gather-vector-4 cpu ( dst src1 src2 src3 src4 rep -- )
 HOOK: %shuffle-vector cpu ( dst src shuffle rep -- )
@@ -239,6 +240,7 @@ HOOK: %and-vector cpu ( dst src1 src2 rep -- )
 HOOK: %andn-vector cpu ( dst src1 src2 rep -- )
 HOOK: %or-vector cpu ( dst src1 src2 rep -- )
 HOOK: %xor-vector cpu ( dst src1 src2 rep -- )
+HOOK: %not-vector cpu ( dst src rep -- )
 HOOK: %shl-vector cpu ( dst src1 src2 rep -- )
 HOOK: %shr-vector cpu ( dst src1 src2 rep -- )
 HOOK: %horizontal-shl-vector cpu ( dst src1 src2 rep -- )
@@ -250,6 +252,7 @@ HOOK: %vector>scalar cpu ( dst src rep -- )
 HOOK: %scalar>vector cpu ( dst src rep -- )
 
 HOOK: %zero-vector-reps cpu ( -- reps )
+HOOK: %fill-vector-reps cpu ( -- reps )
 HOOK: %gather-vector-2-reps cpu ( -- reps )
 HOOK: %gather-vector-4-reps cpu ( -- reps )
 HOOK: %shuffle-vector-reps cpu ( -- reps )
@@ -274,6 +277,7 @@ HOOK: %and-vector-reps cpu ( -- reps )
 HOOK: %andn-vector-reps cpu ( -- reps )
 HOOK: %or-vector-reps cpu ( -- reps )
 HOOK: %xor-vector-reps cpu ( -- reps )
+HOOK: %not-vector-reps cpu ( -- reps )
 HOOK: %shl-vector-reps cpu ( -- reps )
 HOOK: %shr-vector-reps cpu ( -- reps )
 HOOK: %horizontal-shl-vector-reps cpu ( -- reps )

basis/cpu/ppc/ppc.factor

@@ -258,6 +258,7 @@ M: ppc %double>single-float double-rep %copy ;
 
 ! VMX/AltiVec not supported yet
 M: ppc %zero-vector-reps { } ;
+M: ppc %fill-vector-reps { } ;
 M: ppc %gather-vector-2-reps { } ;
 M: ppc %gather-vector-4-reps { } ;
 M: ppc %shuffle-vector-reps { } ;
@@ -282,6 +283,7 @@ M: ppc %and-vector-reps { } ;
 M: ppc %andn-vector-reps { } ;
 M: ppc %or-vector-reps { } ;
 M: ppc %xor-vector-reps { } ;
+M: ppc %not-vector-reps { } ;
 M: ppc %shl-vector-reps { } ;
 M: ppc %shr-vector-reps { } ;
 M: ppc %horizontal-shl-vector-reps { } ;

basis/cpu/x86/x86.factor

@@ -575,6 +575,19 @@ M: x86 %zero-vector-reps
         { sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
     } available-reps ;
 
+M: x86 %fill-vector
+    {
+        { double-2-rep [ dup [ XORPD ] [ CMPEQPD ] 2bi ] }
+        { float-4-rep  [ dup [ XORPS ] [ CMPEQPS ] 2bi ] }
+        [ drop dup PCMPEQB ]
+    } case ;
+
+M: x86 %fill-vector-reps
+    {
+        { sse? { float-4-rep } }
+        { sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
+    } available-reps ;
+
 : unsign-rep ( rep -- rep' )
     {
         { uint-4-rep      int-4-rep }
@@ -1053,6 +1066,16 @@ M: x86 %xor-vector-reps
         { sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
     } available-reps ;
 
+M:: x86 %not-vector ( dst src rep -- )
+    dst rep %fill-vector
+    dst dst src rep %xor-vector ;
+
+M: x86 %not-vector-reps
+    {
+        { sse? { float-4-rep } }
+        { sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
+    } available-reps ;
+
 M: x86 %shl-vector ( dst src1 src2 rep -- )
     [ two-operand ] keep
     {

basis/math/vectors/simd/intrinsics/intrinsics.factor

@@ -44,10 +44,12 @@ SIMD-OP: vbitand
 SIMD-OP: vbitandn
 SIMD-OP: vbitor
 SIMD-OP: vbitxor
+SIMD-OP: vbitnot
 SIMD-OP: vand
 SIMD-OP: vandn
 SIMD-OP: vor
 SIMD-OP: vxor
+SIMD-OP: vnot
 SIMD-OP: vlshift
 SIMD-OP: vrshift
 SIMD-OP: hlshift
@@ -129,10 +131,12 @@ M: vector-rep supported-simd-op?
         { \ (simd-vbitandn) [ %andn-vector-reps           ] }
         { \ (simd-vbitor)   [ %or-vector-reps             ] }
         { \ (simd-vbitxor)  [ %xor-vector-reps            ] }
+        { \ (simd-vbitnot)  [ %not-vector-reps            ] }
         { \ (simd-vand)     [ %and-vector-reps            ] }
         { \ (simd-vandn)    [ %andn-vector-reps           ] }
         { \ (simd-vor)      [ %or-vector-reps             ] }
         { \ (simd-vxor)     [ %xor-vector-reps            ] }
+        { \ (simd-vnot)     [ %not-vector-reps            ] }
         { \ (simd-vlshift)  [ %shl-vector-reps            ] }
         { \ (simd-vrshift)  [ %shr-vector-reps            ] }
         { \ (simd-hlshift)  [ %horizontal-shl-vector-reps ] }

basis/math/vectors/simd/simd-tests.factor

@@ -160,7 +160,7 @@ CONSTANT: simd-classes
     { vlshift vrshift } unique assoc-diff ;
 
 : boolean-ops ( -- words )
-    { vand vandn vor vxor } ;
+    { vand vandn vor vxor vnot } ;
 
 : remove-boolean-words ( alist -- alist' )
     boolean-ops unique assoc-diff ;

basis/math/vectors/specialization/specialization.factor

@@ -86,10 +86,12 @@ H{
     { vbitandn { +vector+ +vector+ -> +vector+ } }
     { vbitor { +vector+ +vector+ -> +vector+ } }
     { vbitxor { +vector+ +vector+ -> +vector+ } }
+    { vbitnot { +vector+ -> +vector+ } }
     { vand { +vector+ +vector+ -> +vector+ } }
     { vandn { +vector+ +vector+ -> +vector+ } }
     { vor { +vector+ +vector+ -> +vector+ } }
     { vxor { +vector+ +vector+ -> +vector+ } }
+    { vnot { +vector+ -> +vector+ } }
     { vlshift { +vector+ +scalar+ -> +vector+ } }
     { vrshift { +vector+ +scalar+ -> +vector+ } }
     { hlshift { +vector+ +literal+ -> +vector+ } }