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vm: More indentation fixes

Slava Pestov 2009-09-14 03:14:48 -05:00
parent 78e143b13c
commit 3db631716f
4 changed files with 115 additions and 116 deletions
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73
vm/cpu-ppc.S
View File

@ -88,11 +88,12 @@ multiply_overflow:
#define RESTORE_FP(register,offset) lfd register,SAVE_AT(offset)(r1) #define RESTORE_FP(register,offset) lfd register,SAVE_AT(offset)(r1)
#define SAVE_V(register,offset) \ #define SAVE_V(register,offset) \
li r2,SAVE_AT(offset) XX \ li r2,SAVE_AT(offset) XX \
stvxl register,r2,r1 stvxl register,r2,r1
#define RESTORE_V(register,offset) \ #define RESTORE_V(register,offset) \
li r2,SAVE_AT(offset) XX \ li r2,SAVE_AT(offset) XX \
lvxl register,r2,r1 lvxl register,r2,r1
#define PROLOGUE \ #define PROLOGUE \
mflr r0 XX /* get caller's return address */ \ mflr r0 XX /* get caller's return address */ \
@ -104,8 +105,6 @@ multiply_overflow:
lwz r1,0(r1) XX /* destroy the stack frame */ \ lwz r1,0(r1) XX /* destroy the stack frame */ \
mtlr r0 /* get ready to return */ mtlr r0 /* get ready to return */
/* We have to save and restore nonvolatile registers because /* We have to save and restore nonvolatile registers because
the Factor compiler treats the entire register file as volatile. */ the Factor compiler treats the entire register file as volatile. */
DEF(void,c_to_factor,(CELL quot)): DEF(void,c_to_factor,(CELL quot)):
@ -288,44 +287,44 @@ DEF(void,flush_icache,(void *start, int len)):
blr blr
DEF(void,primitive_inline_cache_miss,(void)): DEF(void,primitive_inline_cache_miss,(void)):
mflr r6 mflr r6
DEF(void,primitive_inline_cache_miss_tail,(void)): DEF(void,primitive_inline_cache_miss_tail,(void)):
PROLOGUE PROLOGUE
mr r3,r6 mr r3,r6
bl MANGLE(inline_cache_miss) bl MANGLE(inline_cache_miss)
EPILOGUE EPILOGUE
mtctr r3 mtctr r3
bctr bctr
DEF(void,get_ppc_fpu_env,(void*)): DEF(void,get_ppc_fpu_env,(void*)):
mffs f0 mffs f0
stfd f0,0(r3) stfd f0,0(r3)
blr blr
DEF(void,set_ppc_fpu_env,(const void*)): DEF(void,set_ppc_fpu_env,(const void*)):
lfd f0,0(r3) lfd f0,0(r3)
mtfsf 0xff,f0 mtfsf 0xff,f0
blr blr
DEF(void,get_ppc_vmx_env,(void*)): DEF(void,get_ppc_vmx_env,(void*)):
mfvscr v0 mfvscr v0
subi r4,r1,16 subi r4,r1,16
li r5,0xf li r5,0xf
andc r4,r4,r5 andc r4,r4,r5
stvxl v0,0,r4 stvxl v0,0,r4
li r5,0xc li r5,0xc
lwzx r6,r5,r4 lwzx r6,r5,r4
stw r6,0(r3) stw r6,0(r3)
blr blr
DEF(void,set_ppc_vmx_env,(const void*)): DEF(void,set_ppc_vmx_env,(const void*)):
subi r4,r1,16 subi r4,r1,16
li r5,0xf li r5,0xf
andc r4,r4,r5 andc r4,r4,r5
li r5,0xc li r5,0xc
lwz r6,0(r3) lwz r6,0(r3)
stwx r6,r5,r4 stwx r6,r5,r4
lvxl v0,0,r4 lvxl v0,0,r4
mtvscr v0 mtvscr v0
blr blr

28
vm/cpu-x86.32.S
View File

@ -58,26 +58,26 @@ DEF(void,primitive_inline_cache_miss_tail,(void)):
jmp *%eax jmp *%eax
DEF(void,get_sse_env,(void*)): DEF(void,get_sse_env,(void*)):
movl 4(%esp), %eax movl 4(%esp), %eax
stmxcsr (%eax) stmxcsr (%eax)
ret ret
DEF(void,set_sse_env,(const void*)): DEF(void,set_sse_env,(const void*)):
movl 4(%esp), %eax movl 4(%esp), %eax
ldmxcsr (%eax) ldmxcsr (%eax)
ret ret
DEF(void,get_x87_env,(void*)): DEF(void,get_x87_env,(void*)):
movl 4(%esp), %eax movl 4(%esp), %eax
fnstsw (%eax) fnstsw (%eax)
fnstcw 2(%eax) fnstcw 2(%eax)
ret ret
DEF(void,set_x87_env,(const void*)): DEF(void,set_x87_env,(const void*)):
movl 4(%esp), %eax movl 4(%esp), %eax
fnclex fnclex
fldcw 2(%eax) fldcw 2(%eax)
ret ret
#include "cpu-x86.S" #include "cpu-x86.S"

20
vm/cpu-x86.64.S
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@ -89,21 +89,21 @@ DEF(void,primitive_inline_cache_miss_tail,(void)):
jmp *%rax jmp *%rax
DEF(void,get_sse_env,(void*)): DEF(void,get_sse_env,(void*)):
stmxcsr (%rdi) stmxcsr (%rdi)
ret ret
DEF(void,set_sse_env,(const void*)): DEF(void,set_sse_env,(const void*)):
ldmxcsr (%rdi) ldmxcsr (%rdi)
ret ret
DEF(void,get_x87_env,(void*)): DEF(void,get_x87_env,(void*)):
fnstsw (%rdi) fnstsw (%rdi)
fnstcw 2(%rdi) fnstcw 2(%rdi)
ret ret
DEF(void,set_x87_env,(const void*)): DEF(void,set_x87_env,(const void*)):
fnclex fnclex
fldcw 2(%rdi) fldcw 2(%rdi)
ret ret
#include "cpu-x86.S" #include "cpu-x86.S"

110
vm/cpu-x86.S
View File

@ -1,38 +1,38 @@
DEF(void,primitive_fixnum_add,(void)): DEF(void,primitive_fixnum_add,(void)):
mov (DS_REG),ARG0 mov (DS_REG),ARG0
mov -CELL_SIZE(DS_REG),ARG1 mov -CELL_SIZE(DS_REG),ARG1
sub $CELL_SIZE,DS_REG sub $CELL_SIZE,DS_REG
mov ARG1,ARITH_TEMP_1 mov ARG1,ARITH_TEMP_1
add ARG0,ARITH_TEMP_1 add ARG0,ARITH_TEMP_1
jo MANGLE(overflow_fixnum_add) jo MANGLE(overflow_fixnum_add)
mov ARITH_TEMP_1,(DS_REG) mov ARITH_TEMP_1,(DS_REG)
ret ret
DEF(void,primitive_fixnum_subtract,(void)): DEF(void,primitive_fixnum_subtract,(void)):
mov (DS_REG),ARG1 mov (DS_REG),ARG1
mov -CELL_SIZE(DS_REG),ARG0 mov -CELL_SIZE(DS_REG),ARG0
sub $CELL_SIZE,DS_REG sub $CELL_SIZE,DS_REG
mov ARG0,ARITH_TEMP_1 mov ARG0,ARITH_TEMP_1
sub ARG1,ARITH_TEMP_1 sub ARG1,ARITH_TEMP_1
jo MANGLE(overflow_fixnum_subtract) jo MANGLE(overflow_fixnum_subtract)
mov ARITH_TEMP_1,(DS_REG) mov ARITH_TEMP_1,(DS_REG)
ret ret
DEF(void,primitive_fixnum_multiply,(void)): DEF(void,primitive_fixnum_multiply,(void)):
mov (DS_REG),ARITH_TEMP_1 mov (DS_REG),ARITH_TEMP_1
mov ARITH_TEMP_1,DIV_RESULT mov ARITH_TEMP_1,DIV_RESULT
mov -CELL_SIZE(DS_REG),ARITH_TEMP_2 mov -CELL_SIZE(DS_REG),ARITH_TEMP_2
sar $3,ARITH_TEMP_2 sar $3,ARITH_TEMP_2
sub $CELL_SIZE,DS_REG sub $CELL_SIZE,DS_REG
imul ARITH_TEMP_2 imul ARITH_TEMP_2
jo multiply_overflow jo multiply_overflow
mov DIV_RESULT,(DS_REG) mov DIV_RESULT,(DS_REG)
ret ret
multiply_overflow: multiply_overflow:
sar $3,ARITH_TEMP_1 sar $3,ARITH_TEMP_1
mov ARITH_TEMP_1,ARG0 mov ARITH_TEMP_1,ARG0
mov ARITH_TEMP_2,ARG1 mov ARITH_TEMP_2,ARG1
jmp MANGLE(overflow_fixnum_multiply) jmp MANGLE(overflow_fixnum_multiply)
DEF(F_FASTCALL void,c_to_factor,(CELL quot)): DEF(F_FASTCALL void,c_to_factor,(CELL quot)):
PUSH_NONVOLATILE PUSH_NONVOLATILE
@ -77,38 +77,38 @@ DEF(F_FASTCALL void,lazy_jit_compile,(CELL quot)):
DEF(bool,sse_version,(void)): DEF(bool,sse_version,(void)):
mov $0x1,RETURN_REG mov $0x1,RETURN_REG
cpuid cpuid
/* test $0x100000,%ecx /* test $0x100000,%ecx
jnz sse_42 jnz sse_42
test $0x80000,%ecx test $0x80000,%ecx
jnz sse_41 jnz sse_41
test $0x200,%ecx test $0x200,%ecx
jnz ssse_3 */ jnz ssse_3 */
test $0x1,%ecx test $0x1,%ecx
jnz sse_3 jnz sse_3
test $0x4000000,%edx test $0x4000000,%edx
jnz sse_2 jnz sse_2
test $0x2000000,%edx test $0x2000000,%edx
jnz sse_1 jnz sse_1
mov $0,%eax mov $0,%eax
ret ret
sse_42: sse_42:
mov $42,RETURN_REG mov $42,RETURN_REG
ret ret
sse_41: sse_41:
mov $41,RETURN_REG mov $41,RETURN_REG
ret ret
ssse_3: ssse_3:
mov $33,RETURN_REG mov $33,RETURN_REG
ret ret
sse_3: sse_3:
mov $30,RETURN_REG mov $30,RETURN_REG
ret ret
sse_2: sse_2:
mov $20,RETURN_REG mov $20,RETURN_REG
ret ret
sse_1: sse_1:
mov $10,RETURN_REG mov $10,RETURN_REG
ret ret
#ifdef WINDOWS #ifdef WINDOWS
.section .drectve .section .drectve
.ascii " -export:sse_version" .ascii " -export:sse_version"