steve
/
factor
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

change name of 'unsign-rep' to more sensible 'signed-rep'

db4
Joe Groff 2009-11-24 22:44:12 -08:00
parent 9128f1f160
commit 50f7dff422
3 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
basis/compiler/cfg/intrinsics/simd/simd.factor
View File

@ -20,7 +20,7 @@ IN: compiler.cfg.intrinsics.simd
! compound vector ops ! compound vector ops
: sign-bit-mask ( rep -- byte-array ) : sign-bit-mask ( rep -- byte-array )
unsign-rep { signed-rep {
{ char-16-rep [ uchar-array{ { char-16-rep [ uchar-array{
HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80
HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80 HEX: 80
@ -48,7 +48,7 @@ IN: compiler.cfg.intrinsics.simd
} case ; } case ;
: ^load-add-sub-vector ( rep -- dst ) : ^load-add-sub-vector ( rep -- dst )
unsign-rep { signed-rep {
{ float-4-rep [ float-array{ -0.0 0.0 -0.0 0.0 } underlying>> ^^load-constant ] } { float-4-rep [ float-array{ -0.0 0.0 -0.0 0.0 } underlying>> ^^load-constant ] }
{ double-2-rep [ double-array{ -0.0 0.0 } underlying>> ^^load-constant ] } { double-2-rep [ double-array{ -0.0 0.0 } underlying>> ^^load-constant ] }
{ char-16-rep [ char-array{ -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 } underlying>> ^^load-constant ] } { char-16-rep [ char-array{ -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 -1 0 } underlying>> ^^load-constant ] }
@ -115,7 +115,7 @@ IN: compiler.cfg.intrinsics.simd
rep sign-bit-mask ^^load-constant :> sign-bits rep sign-bit-mask ^^load-constant :> sign-bits
src1 sign-bits rep ^^xor-vector src1 sign-bits rep ^^xor-vector
src2 sign-bits rep ^^xor-vector src2 sign-bits rep ^^xor-vector
rep unsign-rep cc ^(compare-vector) rep signed-rep cc ^(compare-vector)
] } ] }
} vv-cc-vector-op ; } vv-cc-vector-op ;
@ -247,7 +247,7 @@ IN: compiler.cfg.intrinsics.simd
] [ ^^vector>scalar ] bi ; ] [ ^^vector>scalar ] bi ;
: ^sum-vector ( src rep -- dst ) : ^sum-vector ( src rep -- dst )
unsign-rep { signed-rep {
{ float-vector-rep [ ^(sum-vector) ] } { float-vector-rep [ ^(sum-vector) ] }
{ int-vector-rep [| src rep | { int-vector-rep [| src rep |
src rep ^unpack-vector-head :> head src rep ^unpack-vector-head :> head

2
basis/cpu/architecture/architecture.factor
View File

@ -95,7 +95,7 @@ double-rep
vector-rep vector-rep
scalar-rep ; scalar-rep ;
: unsign-rep ( rep -- rep' ) : signed-rep ( rep -- rep' )
{ {
{ uint-4-rep int-4-rep } { uint-4-rep int-4-rep }
{ ulonglong-2-rep longlong-2-rep } { ulonglong-2-rep longlong-2-rep }

18
basis/cpu/x86/x86.factor
View File

@ -650,7 +650,7 @@ M: x86 %fill-vector-reps
} available-reps ; } available-reps ;
! M:: x86 %broadcast-vector ( dst src rep -- ) ! M:: x86 %broadcast-vector ( dst src rep -- )
! rep unsign-rep { ! rep signed-rep {
! { float-4-rep [ ! { float-4-rep [
! dst src float-4-rep %copy ! dst src float-4-rep %copy
! dst dst { 0 0 0 0 } SHUFPS ! dst dst { 0 0 0 0 } SHUFPS
@ -687,7 +687,7 @@ M: x86 %fill-vector-reps
! } available-reps ; ! } available-reps ;
M:: x86 %gather-vector-4 ( dst src1 src2 src3 src4 rep -- ) M:: x86 %gather-vector-4 ( dst src1 src2 src3 src4 rep -- )
rep unsign-rep { rep signed-rep {
{ float-4-rep [ { float-4-rep [
dst src1 float-4-rep %copy dst src1 float-4-rep %copy
dst src2 UNPCKLPS dst src2 UNPCKLPS
@ -710,7 +710,7 @@ M: x86 %gather-vector-4-reps
} available-reps ; } available-reps ;
M:: x86 %gather-vector-2 ( dst src1 src2 rep -- ) M:: x86 %gather-vector-2 ( dst src1 src2 rep -- )
rep unsign-rep { rep signed-rep {
{ double-2-rep [ { double-2-rep [
dst src1 double-2-rep %copy dst src1 double-2-rep %copy
dst src2 MOVLHPS dst src2 MOVLHPS
@ -763,7 +763,7 @@ M: x86 %gather-vector-2-reps
M:: x86 %shuffle-vector-imm ( dst src shuffle rep -- ) M:: x86 %shuffle-vector-imm ( dst src shuffle rep -- )
dst src rep %copy dst src rep %copy
dst shuffle rep unsign-rep { dst shuffle rep signed-rep {
{ double-2-rep [ >float-4-shuffle float-4-shuffle ] } { double-2-rep [ >float-4-shuffle float-4-shuffle ] }
{ float-4-rep [ float-4-shuffle ] } { float-4-rep [ float-4-shuffle ] }
{ int-4-rep [ int-4-shuffle ] } { int-4-rep [ int-4-shuffle ] }
@ -786,7 +786,7 @@ M: x86 %shuffle-vector-reps
M: x86 %merge-vector-head M: x86 %merge-vector-head
[ two-operand ] keep [ two-operand ] keep
unsign-rep { signed-rep {
{ double-2-rep [ MOVLHPS ] } { double-2-rep [ MOVLHPS ] }
{ float-4-rep [ UNPCKLPS ] } { float-4-rep [ UNPCKLPS ] }
{ longlong-2-rep [ PUNPCKLQDQ ] } { longlong-2-rep [ PUNPCKLQDQ ] }
@ -797,7 +797,7 @@ M: x86 %merge-vector-head
M: x86 %merge-vector-tail M: x86 %merge-vector-tail
[ two-operand ] keep [ two-operand ] keep
unsign-rep { signed-rep {
{ double-2-rep [ UNPCKHPD ] } { double-2-rep [ UNPCKHPD ] }
{ float-4-rep [ UNPCKHPS ] } { float-4-rep [ UNPCKHPS ] }
{ longlong-2-rep [ PUNPCKHQDQ ] } { longlong-2-rep [ PUNPCKHQDQ ] }
@ -826,7 +826,7 @@ M: x86 %signed-pack-vector-reps
M: x86 %unsigned-pack-vector M: x86 %unsigned-pack-vector
[ two-operand ] keep [ two-operand ] keep
unsign-rep { signed-rep {
{ int-4-rep [ PACKUSDW ] } { int-4-rep [ PACKUSDW ] }
{ short-8-rep [ PACKUSWB ] } { short-8-rep [ PACKUSWB ] }
} case ; } case ;
@ -896,7 +896,7 @@ M: x86 %float>integer-vector-reps
} case ; } case ;
:: (%compare-int-vector) ( dst src rep int64 int32 int16 int8 -- ) :: (%compare-int-vector) ( dst src rep int64 int32 int16 int8 -- )
rep unsign-rep :> rep' rep signed-rep :> rep'
dst src rep' { dst src rep' {
{ longlong-2-rep [ int64 call ] } { longlong-2-rep [ int64 call ] }
{ int-4-rep [ int32 call ] } { int-4-rep [ int32 call ] }
@ -1173,7 +1173,7 @@ M: x86 %dot-vector-reps
M: x86 %horizontal-add-vector ( dst src1 src2 rep -- ) M: x86 %horizontal-add-vector ( dst src1 src2 rep -- )
[ two-operand ] keep [ two-operand ] keep
unsign-rep { signed-rep {
{ float-4-rep [ HADDPS ] } { float-4-rep [ HADDPS ] }
{ double-2-rep [ HADDPD ] } { double-2-rep [ HADDPD ] }
{ int-4-rep [ PHADDD ] } { int-4-rep [ PHADDD ] }