Starting to update PowerPC backend for recent VM changes (untested)
Slava Pestov
parent
0fd3c78157
commit
6266b41325
3
Makefile
3
Makefile
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@ -212,6 +212,9 @@ vm/ffi_test.o: vm/ffi_test.c
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.cpp.o:
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$(TOOLCHAIN_PREFIX)$(CPP) -c $(CFLAGS) -o $@ $<
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.S.o:
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$(TOOLCHAIN_PREFIX)$(CC) -x assembler-with-cpp -c $(CFLAGS) -o $@ $<
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.mm.o:
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$(TOOLCHAIN_PREFIX)$(CPP) -c $(CFLAGS) -o $@ $<
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@ -1,9 +1,10 @@
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! Copyright (C) 2007, 2009 Slava Pestov.
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! Copyright (C) 2007, 2010 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: bootstrap.image.private kernel kernel.private namespaces
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system cpu.ppc.assembler compiler.codegen.fixup compiler.units
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compiler.constants math math.private layouts words vocabs
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slots.private locals locals.backend generic.single.private fry ;
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compiler.constants math math.private math.ranges layouts words vocabs
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slots.private locals locals.backend generic.single.private fry
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sequences ;
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FROM: cpu.ppc.assembler => B ;
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IN: bootstrap.ppc
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@ -13,28 +14,88 @@ big-endian on
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CONSTANT: ds-reg 13
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CONSTANT: rs-reg 14
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CONSTANT: vm-reg 15
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CONSTANT: ctx-reg 16
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: factor-area-size ( -- n ) 4 bootstrap-cells ;
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: factor-area-size ( -- n ) 16 ;
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: stack-frame ( -- n )
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factor-area-size c-area-size + 4 bootstrap-cells align ;
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reserved-size
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factor-area-size +
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16 align ;
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: next-save ( -- n ) stack-frame bootstrap-cell - ;
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: xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;
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: next-save ( -- n ) stack-frame 4 - ;
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: xt-save ( -- n ) stack-frame 8 - ;
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: param-size ( -- n ) 32 ;
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: save-at ( m -- n ) reserved-size + param-size + ;
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: save-int ( register offset -- ) [ 1 ] dip save-at STW ;
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: restore-int ( register offset -- ) [ 1 ] dip save-at LWZ ;
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: save-fp ( register offset -- ) [ 1 ] dip save-at STFD ;
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: restore-fp ( register offset -- ) [ 1 ] dip save-at LFD ;
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: save-vec ( register offset -- ) save-at 2 LI 2 1 STVXL ;
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: restore-vec ( register offset -- ) save-at 2 LI 2 1 LVXL ;
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: nv-int-regs ( -- seq ) 13 31 [a,b] ;
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: nv-fp-regs ( -- seq ) 14 31 [a,b] ;
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: nv-vec-regs ( -- seq ) 20 31 [a,b] ;
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: saved-int-regs-size ( -- n ) 96 ;
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: saved-fp-regs-size ( -- n ) 144 ;
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: saved-vec-regs-size ( -- n ) 208 ;
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: callback-frame-size ( -- n )
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reserved-size
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param-size +
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saved-int-regs-size +
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saved-fp-regs-size +
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saved-vec-regs-size +
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16 align ;
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[
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0 MFLR
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1 1 callback-frame-size neg STWU
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0 1 callback-frame-size lr-save + STW
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nv-int-regs [ cells save-int ] each-index
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nv-fp-regs [ 8 * 80 + save-fp ] each-index
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nv-vec-regs [ 16 * 224 + save-vec ] each-index
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0 vm-reg LOAD32 rt-vm rc-absolute-ppc-2/2 jit-rel
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0 2 LOAD32 rc-absolute-ppc-2/2 rt-xt jit-rel
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2 MTLR
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BLRL
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nv-vec-regs [ 16 * 224 + restore-vec ] each-index
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nv-fp-regs [ 8 * 80 + restore-fp ] each-index
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nv-int-regs [ cells restore-int ] each-index
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0 1 callback-frame-size lr-save + LWZ
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1 1 0 LWZ
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0 MTLR
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BLR
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] callback-stub jit-define
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: jit-conditional* ( test-quot false-quot -- )
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[ '[ bootstrap-cell /i 1 + @ ] ] dip jit-conditional ; inline
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[ '[ 4 /i 1 + @ ] ] dip jit-conditional ; inline
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: jit-load-context ( -- )
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ctx-reg vm-reg vm-context-offset LWZ ;
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: jit-save-context ( -- )
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4 vm-reg 0 LWZ
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1 4 0 STW
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ds-reg 4 8 STW
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rs-reg 4 12 STW ;
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jit-load-context
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1 2 context-callstack-top-offset STW
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ds-reg ctx-reg context-datastack-offset STW
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rs-reg ctx-reg context-retainstack-offset STW ;
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: jit-restore-context ( -- )
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4 vm-reg 0 LWZ
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ds-reg 4 8 LWZ
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rs-reg 4 12 LWZ ;
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jit-load-context
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ds-reg ctx-reg context-datastack-offset LWZ
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rs-reg ctx-reg context-retainstack-offset LWZ ;
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[
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel
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@ -181,7 +242,7 @@ CONSTANT: vm-reg 15
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load-tag
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0 4 tuple type-number tag-fixnum CMPI
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[ BNE ]
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[ 4 3 tuple type-number neg bootstrap-cell + LWZ ]
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[ 4 3 tuple type-number neg 4 + LWZ ]
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jit-conditional*
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] pic-tuple jit-define
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@ -230,7 +291,7 @@ CONSTANT: vm-reg 15
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! key = hashcode(class)
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5 4 1 SRAWI
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! key &= cache.length - 1
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5 5 mega-cache-size get 1 - bootstrap-cell * ANDI
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5 5 mega-cache-size get 1 - 4 * ANDI
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! cache += array-start-offset
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3 3 array-start-offset ADDI
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! cache += key
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@ -245,7 +306,7 @@ CONSTANT: vm-reg 15
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5 4 0 LWZ
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5 5 1 ADDI
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5 4 0 STW
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! ... goto get(cache + bootstrap-cell)
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! ... goto get(cache + 4)
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3 3 4 LWZ
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3 3 word-xt-offset LWZ
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3 MTCTR
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@ -255,19 +316,12 @@ CONSTANT: vm-reg 15
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! fall-through on miss
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] mega-lookup jit-define
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[
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0 2 LOAD32 rc-absolute-ppc-2/2 rt-xt jit-rel
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2 MTCTR
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BCTR
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] callback-stub jit-define
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! ! ! Sub-primitives
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! Quotations and words
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[
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3 ds-reg 0 LWZ
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ds-reg dup 4 SUBI
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4 vm-reg MR
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5 3 quot-xt-offset LWZ
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]
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[ 5 MTLR BLRL ]
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@ -288,6 +342,75 @@ CONSTANT: vm-reg 15
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4 MTCTR BCTR
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] jit-execute jit-define
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! Special primitives
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[
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jit-restore-context
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! Save ctx->callstack_bottom
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1 ctx-reg context-callstack-bottom-offset STW
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! Call quotation
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5 3 quot-xt-offset LWZ
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5 MTLR
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BLRL
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jit-save-context
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] \ c-to-factor define-sub-primitive
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[
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! Unwind stack frames
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1 4 MR
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! Load ds and rs registers
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jit-restore-context
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! We have changed the stack; load return address again
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0 1 stack-frame lr-save + LWZ
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0 MTLR
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! Call quotation
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4 3 quot-xt-offset LWZ
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4 MTCTR
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BCTR
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] \ unwind-native-frames define-sub-primitive
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[
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! Load callstack object
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6 ds-reg 0 LWZ
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ds-reg ds-reg 4 SUBI
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! Get ctx->callstack_bottom
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jit-load-context
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3 ctx-reg context-callstack-bottom-offset LWZ
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! Get top of callstack object -- 'src' for memcpy
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4 6 callstack-top-offset ADDI
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! Get callstack length, in bytes --- 'len' for memcpy
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5 6 callstack-length-offset LWZ
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5 5 tag-bits get SRAWI
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! Compute new stack pointer -- 'dst' for memcpy
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3 3 5 SUBF
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! Install new stack pointer
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1 3 MR
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! Call memcpy; arguments are now in the correct registers
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1 1 -64 STWU
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0 2 LOAD32 "factor_memcpy" f rc-absolute-ppc-2/2 jit-dlsym
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2 MTLR
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BLRL
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1 1 0 LWZ
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! Return with new callstack
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0 1 lr-save stack-frame + LWZ
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0 MTLR
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BLR
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] \ set-callstack define-sub-primitive
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[
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jit-save-context
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4 vm-reg MR
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2 0 LOAD32 "lazy_jit_compile" f rc-absolute-ppc-2/2 jit-dlsym
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2 MTLR
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BLRL
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5 3 quot-xt-offset LWZ
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]
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[ 5 MTLR BLRL ]
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[ 5 MTCTR BCTR ]
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\ lazy-jit-compile define-combinator-primitive
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! Objects
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[
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3 ds-reg 0 LWZ
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@ -1,10 +1,10 @@
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! Copyright (C) 2007, 2008 Slava Pestov.
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! Copyright (C) 2007, 2010 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: parser layouts system kernel sequences ;
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USING: parser system kernel sequences ;
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IN: bootstrap.ppc
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: c-area-size ( -- n ) 10 bootstrap-cells ;
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: lr-save ( -- n ) bootstrap-cell ;
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: reserved-size ( -- n ) 24 ;
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: lr-save ( -- n ) 4 ;
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<< "vocab:cpu/ppc/bootstrap.factor" parse-file suffix! >>
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call
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@ -1,10 +1,10 @@
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! Copyright (C) 2007, 2008 Slava Pestov.
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! Copyright (C) 2007, 2010 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: parser layouts system kernel sequences ;
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USING: parser system kernel sequences ;
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IN: bootstrap.ppc
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: c-area-size ( -- n ) 14 bootstrap-cells ;
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: lr-save ( -- n ) 2 bootstrap-cells ;
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: reserved-size ( -- n ) 24 ;
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: lr-save ( -- n ) 8 ;
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<< "vocab:cpu/ppc/bootstrap.factor" parse-file suffix! >>
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call
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@ -1 +1 @@
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PLAF_DLL_OBJS += vm/cpu-ppc.o
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400
vm/cpu-ppc.S
400
vm/cpu-ppc.S
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@ -1,367 +1,73 @@
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/* Parts of this file were snarfed from SBCL src/runtime/ppc-assem.S, which is
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in the public domain. */
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#if defined(__APPLE__) || (defined(WINDOWS) && !defined(__arm__))
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#define MANGLE(sym) _##sym
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#if defined(__APPLE__)
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#define MANGLE(sym) _##sym
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#define XX @
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#else
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#define MANGLE(sym) sym
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#endif
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/* Apple's PPC assembler is out of date? */
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#if defined(__APPLE__) && defined(__ppc__)
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#define XX @
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#else
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#define XX ;
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#define MANGLE(sym) sym
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#define XX ;
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#endif
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/* The returns and args are just for documentation */
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#define DEF(returns,symbol,args) .globl MANGLE(symbol) XX \
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MANGLE(symbol)
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#define DS_REG r13
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#define RS_REG r14
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#define VM_REG r15
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#define CALL_OR_JUMP_QUOT \
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lwz r11,12(r3) /* load quotation-xt slot */ XX \
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#define CALL_QUOT \
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CALL_OR_JUMP_QUOT XX \
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mtlr r11 /* prepare to call XT with quotation in r3 */ XX \
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blrl /* go */
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#define JUMP_QUOT \
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CALL_OR_JUMP_QUOT XX \
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mtctr r11 /* prepare to call XT with quotation in r3 */ XX \
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bctr /* go */
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#define PARAM_SIZE 32
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#define SAVED_INT_REGS_SIZE 96
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#define SAVED_FP_REGS_SIZE 144
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#define SAVED_V_REGS_SIZE 208
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#define FRAME (RESERVED_SIZE + PARAM_SIZE + SAVED_INT_REGS_SIZE + SAVED_FP_REGS_SIZE + SAVED_V_REGS_SIZE + 8)
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#if defined( __APPLE__)
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#define LR_SAVE 8
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#define RESERVED_SIZE 24
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#else
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#define LR_SAVE 4
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#define RESERVED_SIZE 8
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#endif
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#define SAVE_LR(reg) stw reg,(LR_SAVE + FRAME)(r1)
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#define LOAD_LR(reg) lwz reg,(LR_SAVE + FRAME)(r1)
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#define SAVE_AT(offset) (RESERVED_SIZE + PARAM_SIZE + 4 * offset)
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#define SAVE_INT(register,offset) stw register,SAVE_AT(offset)(r1)
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#define RESTORE_INT(register,offset) lwz register,SAVE_AT(offset)(r1)
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#define SAVE_FP(register,offset) stfd register,SAVE_AT(offset)(r1)
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#define RESTORE_FP(register,offset) lfd register,SAVE_AT(offset)(r1)
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#define SAVE_V(register,offset) \
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li r2,SAVE_AT(offset) XX \
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stvxl register,r2,r1
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#define RESTORE_V(register,offset) \
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li r2,SAVE_AT(offset) XX \
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lvxl register,r2,r1
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#define PROLOGUE \
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mflr r0 XX /* get caller's return address */ \
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stwu r1,-FRAME(r1) XX /* create a stack frame to hold non-volatile registers */ \
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SAVE_LR(r0)
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#define EPILOGUE \
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LOAD_LR(r0) XX \
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lwz r1,0(r1) XX /* destroy the stack frame */ \
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mtlr r0 /* get ready to return */
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/* We have to save and restore nonvolatile registers because
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the Factor compiler treats the entire register file as volatile. */
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DEF(void,c_to_factor,(cell quot, void *vm)):
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PROLOGUE
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SAVE_INT(r13,0)
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SAVE_INT(r14,1)
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SAVE_INT(VM_REG,2)
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SAVE_INT(r16,3)
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SAVE_INT(r17,4)
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SAVE_INT(r18,5)
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SAVE_INT(r19,6)
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SAVE_INT(r20,7)
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SAVE_INT(r21,8)
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SAVE_INT(r22,9)
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SAVE_INT(r23,10)
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SAVE_INT(r24,11)
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SAVE_INT(r25,12)
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SAVE_INT(r26,13)
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SAVE_INT(r27,14)
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SAVE_INT(r28,15)
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SAVE_INT(r29,16)
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SAVE_INT(r30,17)
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SAVE_INT(r31,18)
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SAVE_FP(f14,20)
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SAVE_FP(f15,22)
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SAVE_FP(f16,24)
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SAVE_FP(f17,26)
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SAVE_FP(f18,28)
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SAVE_FP(f19,30)
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SAVE_FP(f20,32)
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SAVE_FP(f21,34)
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SAVE_FP(f22,36)
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SAVE_FP(f23,38)
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SAVE_FP(f24,40)
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SAVE_FP(f25,42)
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SAVE_FP(f26,44)
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SAVE_FP(f27,46)
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SAVE_FP(f28,48)
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SAVE_FP(f29,50)
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SAVE_FP(f30,52)
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SAVE_FP(f31,54)
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SAVE_V(v20,56)
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SAVE_V(v21,60)
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SAVE_V(v22,64)
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SAVE_V(v23,68)
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SAVE_V(v24,72)
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SAVE_V(v25,76)
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SAVE_V(v26,80)
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SAVE_V(v27,84)
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SAVE_V(v28,88)
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SAVE_V(v29,92)
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SAVE_V(v30,96)
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SAVE_V(v31,100)
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/* r4 vm ptr preserved */
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mfvscr v0
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li r2,SAVE_AT(104)
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stvxl v0,r2,r1
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addi r2,r2,0xc
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lwzx r5,r2,r1
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lis r6,0x1
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andc r5,r5,r6
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stwx r5,r2,r1
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subi r2,r2,0xc
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lvxl v0,r2,r1
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mtvscr v0
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/* Load context */
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mr VM_REG,r4
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lwz r16,0(VM_REG)
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/* Load ctx->datastack */
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lwz DS_REG,8(r16)
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/* Load ctx->retainstack */
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lwz RS_REG,12(r16)
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/* Save ctx->callstack_bottom */
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stw r1,4(r16)
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CALL_QUOT
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/* Load context */
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lwz r16,0(VM_REG)
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/* Save ctx->datastack */
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stw DS_REG,8(r16)
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|
||||
/* Save ctx->retainstack */
|
||||
stw RS_REG,12(r16)
|
||||
|
||||
RESTORE_V(v0,104)
|
||||
mtvscr v0
|
||||
|
||||
RESTORE_V(v31,100)
|
||||
RESTORE_V(v30,96)
|
||||
RESTORE_V(v29,92)
|
||||
RESTORE_V(v28,88)
|
||||
RESTORE_V(v27,84)
|
||||
RESTORE_V(v26,80)
|
||||
RESTORE_V(v25,76)
|
||||
RESTORE_V(v24,72)
|
||||
RESTORE_V(v23,68)
|
||||
RESTORE_V(v22,64)
|
||||
RESTORE_V(v21,60)
|
||||
RESTORE_V(v20,56)
|
||||
|
||||
RESTORE_FP(f31,54)
|
||||
RESTORE_FP(f30,52)
|
||||
RESTORE_FP(f29,50)
|
||||
RESTORE_FP(f28,48)
|
||||
RESTORE_FP(f27,46)
|
||||
RESTORE_FP(f26,44)
|
||||
RESTORE_FP(f25,42)
|
||||
RESTORE_FP(f24,40)
|
||||
RESTORE_FP(f23,38)
|
||||
RESTORE_FP(f22,36)
|
||||
RESTORE_FP(f21,34)
|
||||
RESTORE_FP(f20,32)
|
||||
RESTORE_FP(f19,30)
|
||||
RESTORE_FP(f18,28)
|
||||
RESTORE_FP(f17,26)
|
||||
RESTORE_FP(f16,24)
|
||||
RESTORE_FP(f15,22)
|
||||
RESTORE_FP(f14,20)
|
||||
|
||||
RESTORE_INT(r31,18)
|
||||
RESTORE_INT(r30,17)
|
||||
RESTORE_INT(r29,16)
|
||||
RESTORE_INT(r28,15)
|
||||
RESTORE_INT(r27,14)
|
||||
RESTORE_INT(r26,13)
|
||||
RESTORE_INT(r25,12)
|
||||
RESTORE_INT(r24,11)
|
||||
RESTORE_INT(r23,10)
|
||||
RESTORE_INT(r22,9)
|
||||
RESTORE_INT(r21,8)
|
||||
RESTORE_INT(r20,7)
|
||||
RESTORE_INT(r19,6)
|
||||
RESTORE_INT(r18,5)
|
||||
RESTORE_INT(r17,4)
|
||||
RESTORE_INT(r16,3)
|
||||
RESTORE_INT(VM_REG,2)
|
||||
RESTORE_INT(r14,1)
|
||||
RESTORE_INT(r13,0)
|
||||
|
||||
EPILOGUE
|
||||
blr
|
||||
|
||||
DEF(void,set_callstack,(void *vm, stack_frame *to, stack_frame *from, cell length, void *memcpy)):
|
||||
/* Save VM pointer in non-volatile register */
|
||||
mr VM_REG,r3
|
||||
|
||||
/* Compute new stack pointer */
|
||||
sub r1,r4,r6
|
||||
|
||||
/* Call memcpy() */
|
||||
mr r3,r1
|
||||
mr r4,r5
|
||||
mr r5,r6
|
||||
stwu r1,-64(r1)
|
||||
mtlr r7
|
||||
blrl
|
||||
lwz r1,0(r1)
|
||||
|
||||
/* Load context */
|
||||
lwz r16,0(VM_REG)
|
||||
|
||||
/* Load ctx->datastack */
|
||||
lwz DS_REG,8(r16)
|
||||
|
||||
/* Load ctx->retainstack */
|
||||
lwz RS_REG,12(r16)
|
||||
|
||||
/* We have changed the stack; load return address again */
|
||||
lwz r0,LR_SAVE(r1)
|
||||
mtlr r0
|
||||
blr
|
||||
|
||||
DEF(void,throw_impl,(cell quot, void *new_stack, void *vm)):
|
||||
/* compute new stack pointer */
|
||||
mr r1,r4
|
||||
|
||||
/* make vm ptr 2nd arg in case quot->xt == lazy_jit_compile */
|
||||
mr r4,r5
|
||||
|
||||
/* Load context */
|
||||
mr VM_REG,r5
|
||||
lwz r16,0(VM_REG)
|
||||
|
||||
/* Load ctx->datastack */
|
||||
lwz DS_REG,8(r16)
|
||||
|
||||
/* Load ctx->retainstack */
|
||||
lwz RS_REG,12(r16)
|
||||
|
||||
/* We have changed the stack; load return address again */
|
||||
lwz r0,LR_SAVE(r1)
|
||||
mtlr r0
|
||||
|
||||
/* Call the quotation */
|
||||
JUMP_QUOT
|
||||
|
||||
DEF(void,lazy_jit_compile_impl,(cell quot, void *vm)):
|
||||
/* Load context */
|
||||
mr VM_REG,r4
|
||||
lwz r16,0(VM_REG)
|
||||
|
||||
/* Save ctx->datastack */
|
||||
stw DS_REG,8(r16)
|
||||
|
||||
/* Save ctx->retainstack */
|
||||
stw RS_REG,12(r16)
|
||||
|
||||
/* Save ctx->callstack_top */
|
||||
stw r1,0(r16)
|
||||
|
||||
/* Compile quotation */
|
||||
PROLOGUE
|
||||
bl MANGLE(lazy_jit_compile)
|
||||
EPILOGUE
|
||||
|
||||
/* Call the quotation */
|
||||
JUMP_QUOT
|
||||
|
||||
/* Thanks to Joshua Grams for this code.
|
||||
|
||||
On PowerPC processors, we must flush the instruction cache manually
|
||||
after writing to the code heap. */
|
||||
|
||||
DEF(void,flush_icache,(void *start, int len)):
|
||||
/* compute number of cache lines to flush */
|
||||
add r4,r4,r3
|
||||
clrrwi r3,r3,5 /* align addr to next lower cache line boundary */
|
||||
sub r4,r4,r3 /* then n_lines = (len + 0x1f) / 0x20 */
|
||||
addi r4,r4,0x1f
|
||||
srwi. r4,r4,5 /* note '.' suffix */
|
||||
beqlr /* if n_lines == 0, just return. */
|
||||
mtctr r4 /* flush cache lines */
|
||||
0: dcbf 0,r3 /* for each line... */
|
||||
sync
|
||||
icbi 0,r3
|
||||
addi r3,r3,0x20
|
||||
bdnz 0b
|
||||
sync /* finish up */
|
||||
isync
|
||||
blr
|
||||
DEF(void,flush_icache,(void*, int)):
|
||||
/* compute number of cache lines to flush */
|
||||
add r4,r4,r3
|
||||
/* align addr to next lower cache line boundary */
|
||||
clrrwi r3,r3,5
|
||||
/* then n_lines = (len + 0x1f) / 0x20 */
|
||||
sub r4,r4,r3
|
||||
addi r4,r4,0x1f
|
||||
/* note '.' suffix */
|
||||
srwi. r4,r4,5
|
||||
/* if n_lines == 0, just return. */
|
||||
beqlr
|
||||
/* flush cache lines */
|
||||
mtctr r4
|
||||
/* for each line... */
|
||||
0: dcbf 0,r3
|
||||
sync
|
||||
icbi 0,r3
|
||||
addi r3,r3,0x20
|
||||
bdnz 0b
|
||||
/* finish up */
|
||||
sync
|
||||
isync
|
||||
blr
|
||||
|
||||
DEF(void,get_ppc_fpu_env,(void*)):
|
||||
mffs f0
|
||||
stfd f0,0(r3)
|
||||
blr
|
||||
mffs f0
|
||||
stfd f0,0(r3)
|
||||
blr
|
||||
|
||||
DEF(void,set_ppc_fpu_env,(const void*)):
|
||||
lfd f0,0(r3)
|
||||
mtfsf 0xff,f0
|
||||
blr
|
||||
lfd f0,0(r3)
|
||||
mtfsf 0xff,f0
|
||||
blr
|
||||
|
||||
DEF(void,get_ppc_vmx_env,(void*)):
|
||||
mfvscr v0
|
||||
subi r4,r1,16
|
||||
li r5,0xf
|
||||
andc r4,r4,r5
|
||||
stvxl v0,0,r4
|
||||
li r5,0xc
|
||||
lwzx r6,r5,r4
|
||||
stw r6,0(r3)
|
||||
blr
|
||||
mfvscr v0
|
||||
subi r4,r1,16
|
||||
li r5,0xf
|
||||
andc r4,r4,r5
|
||||
stvxl v0,0,r4
|
||||
li r5,0xc
|
||||
lwzx r6,r5,r4
|
||||
stw r6,0(r3)
|
||||
blr
|
||||
|
||||
DEF(void,set_ppc_vmx_env,(const void*)):
|
||||
subi r4,r1,16
|
||||
li r5,0xf
|
||||
andc r4,r4,r5
|
||||
li r5,0xc
|
||||
lwz r6,0(r3)
|
||||
stwx r6,r5,r4
|
||||
lvxl v0,0,r4
|
||||
mtvscr v0
|
||||
blr
|
||||
subi r4,r1,16
|
||||
li r5,0xf
|
||||
andc r4,r4,r5
|
||||
li r5,0xc
|
||||
lwz r6,0(r3)
|
||||
stwx r6,r5,r4
|
||||
lvxl v0,0,r4
|
||||
mtvscr v0
|
||||
blr
|
||||
|
|
|
|||
Loading…
Reference in New Issue