From 78fe8bf1dc73e77689c8616da07e08a7ba80e07c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Lindqvist?= Date: Tue, 16 Jun 2015 15:02:58 +0200 Subject: [PATCH] compiler.cfg.linear-scan.*: dont use a hashtable here, it fixes register allocation so it's always in the same order as machine-registers --- .../allocation/allocation-tests.factor | 30 ++++++++++++++----- .../linear-scan/allocation/allocation.factor | 11 ++++--- .../linear-scan/allocation/state/state.factor | 6 +--- 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/basis/compiler/cfg/linear-scan/allocation/allocation-tests.factor b/basis/compiler/cfg/linear-scan/allocation/allocation-tests.factor index 18ba351dbf..715bcde51c 100644 --- a/basis/compiler/cfg/linear-scan/allocation/allocation-tests.factor +++ b/basis/compiler/cfg/linear-scan/allocation/allocation-tests.factor @@ -4,7 +4,7 @@ compiler.cfg.linear-scan.live-intervals cpu.architecture cpu.x86.assembler.operands heaps kernel namespaces system tools.test ; IN: compiler.cfg.linear-scan.allocation.tests -: unassigned-interval ( -- live-interval ) +: interval-[30,46] ( -- live-interval ) T{ live-interval-state { vreg 49 } { start 30 } { end 46 } @@ -18,17 +18,31 @@ IN: compiler.cfg.linear-scan.allocation.tests { reg-class int-regs } } clone ; +: interval-[30,60] ( -- live-interval ) + T{ live-interval-state + { vreg 25 } + { start 30 } { end 60 } + { reg-class int-regs } + { reg RAX } + } ; + cpu x86.64? [ ! assign-registers - { R8 } [ - { { int-regs V{ } } { float-regs V{ } } } active-intervals set - unassigned-interval dup machine-registers assign-register reg>> + { RAX } [ + f machine-registers init-allocator + interval-[30,46] dup machine-registers assign-register reg>> ] unit-test ! register-status - { { R8 1/0. } } [ - { { int-regs V{ } } { float-regs V{ } } } active-intervals set - unassigned-interval machine-registers register-status + { { RAX 1/0. } } [ + f machine-registers init-allocator + interval-[30,46] machine-registers register-status + ] unit-test + + { { RCX 1/0. } } [ + f machine-registers init-allocator + interval-[30,60] add-active + interval-[30,46] machine-registers register-status ] unit-test ] when @@ -83,7 +97,7 @@ cpu x86.64? [ unhandled-min-heap set f f cfg set 40 progress set - T{ sync-point { n 40 } } unassigned-interval spill-at-sync-point + T{ sync-point { n 40 } } interval-[30,46] spill-at-sync-point ] unit-test ! spill-at-sync-point? diff --git a/basis/compiler/cfg/linear-scan/allocation/allocation.factor b/basis/compiler/cfg/linear-scan/allocation/allocation.factor index a0b538ae84..c90f896526 100644 --- a/basis/compiler/cfg/linear-scan/allocation/allocation.factor +++ b/basis/compiler/cfg/linear-scan/allocation/allocation.factor @@ -1,6 +1,6 @@ ! Copyright (C) 2008, 2010 Slava Pestov. ! See http://factorcode.org/license.txt for BSD license. -USING: accessors assocs combinators combinators.short-circuit +USING: accessors arrays assocs combinators combinators.short-circuit compiler.cfg.linear-scan.allocation.spilling compiler.cfg.linear-scan.allocation.state compiler.cfg.linear-scan.live-intervals compiler.utilities fry @@ -18,10 +18,13 @@ IN: compiler.cfg.linear-scan.allocation _ add-use-position ] each ; +: free-positions ( registers reg-class -- avail-registers ) + of [ 1/0. 2array ] map ; + : register-status ( new registers -- free-pos ) - over reg-class>> free-positions - [ inactive-positions ] [ active-positions ] [ nip ] 2tri - >alist alist-max ; + over reg-class>> free-positions [ + [ inactive-positions ] [ active-positions ] 2bi + ] keep alist-max ; : no-free-registers? ( result -- ? ) second 0 = ; inline diff --git a/basis/compiler/cfg/linear-scan/allocation/state/state.factor b/basis/compiler/cfg/linear-scan/allocation/state/state.factor index 6d218e2c11..8dd96e8d30 100644 --- a/basis/compiler/cfg/linear-scan/allocation/state/state.factor +++ b/basis/compiler/cfg/linear-scan/allocation/state/state.factor @@ -3,8 +3,7 @@ USING: accessors arrays assocs combinators compiler.cfg compiler.cfg.instructions compiler.cfg.linear-scan.live-intervals compiler.cfg.registers -cpu.architecture fry heaps kernel linked-assocs math -math.order namespaces sequences ; +cpu.architecture fry heaps kernel math math.order namespaces sequences ; FROM: assocs => change-at ; IN: compiler.cfg.linear-scan.allocation.state @@ -140,9 +139,6 @@ SYMBOL: spill-slots H{ } clone spill-slots set -1 progress set ; -: free-positions ( registers reg-class -- assoc ) - of [ 1/0. ] H{ } map>assoc ; - : add-use-position ( n reg assoc -- ) [ [ min ] when* ] change-at ;