compiler.cfg.instructions: ##bit-count insn

basis/compiler/cfg/instructions/instructions.factor

@@ -219,6 +219,10 @@ PURE-INSN: ##log2
 def: dst/int-rep
 use: src/int-rep ;
 
+PURE-INSN: ##bit-count
+def: dst/int-rep
+use: src/int-rep ;
+
 ! Float arithmetic
 PURE-INSN: ##add-float
 def: dst/double-rep

basis/compiler/codegen/codegen.factor

@@ -162,6 +162,7 @@ CODEGEN: ##max %max
 CODEGEN: ##not %not
 CODEGEN: ##neg %neg
 CODEGEN: ##log2 %log2
+CODEGEN: ##bit-count %bit-count
 CODEGEN: ##copy %copy
 CODEGEN: ##tagged>integer %tagged>integer
 CODEGEN: ##add-float %add-float

basis/cpu/architecture/architecture.factor

@@ -270,6 +270,7 @@ HOOK: %max     cpu ( dst src1 src2 -- )
 HOOK: %not     cpu ( dst src -- )
 HOOK: %neg     cpu ( dst src -- )
 HOOK: %log2    cpu ( dst src -- )
+HOOK: %bit-count cpu ( dst src -- )
 
 HOOK: %copy cpu ( dst src rep -- )
 

basis/cpu/x86/x86.factor

@@ -164,6 +164,7 @@ M: x86 %max     int-rep two-operand [ CMP ] [ CMOVL ] 2bi ;
 M: x86 %not     int-rep one-operand NOT ;
 M: x86 %neg     int-rep one-operand NEG ;
 M: x86 %log2    BSR ;
+M: x86 %bit-count POPCNT ;
 
 ! A bit of logic to avoid using MOVSS/MOVSD for reg-reg moves
 ! since this induces partial register stalls