compiler.cfg.linear-scan: Get cycle breaking in resolve pass to work by allocating a spare spill slot for this purpose
Slava Pestov
parent
f14a61fac2
commit
a452f32e3a
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@ -261,4 +261,3 @@ INSN: _reload dst class n ;
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INSN: _copy dst src class ;
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INSN: _spill-counts counts ;
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SYMBOL: spill-temp
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@ -206,6 +206,56 @@ check-assignment? on
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} 5 split-before-use [ f >>split-next ] bi@
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] unit-test
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[
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 0 }
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{ end 4 }
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{ uses V{ 0 1 4 } }
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{ ranges V{ T{ live-range f 0 4 } } }
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}
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 5 }
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{ end 10 }
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{ uses V{ 5 10 } }
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{ ranges V{ T{ live-range f 5 10 } } }
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}
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] [
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 0 }
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{ end 10 }
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{ uses V{ 0 1 10 } }
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{ ranges V{ T{ live-range f 0 10 } } }
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} 5 split-before-use [ f >>split-next ] bi@
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] unit-test
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[
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 0 }
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{ end 4 }
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{ uses V{ 0 1 4 } }
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{ ranges V{ T{ live-range f 0 4 } } }
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}
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 5 }
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{ end 10 }
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{ uses V{ 5 10 } }
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{ ranges V{ T{ live-range f 5 10 } } }
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}
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] [
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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{ start 0 }
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{ end 10 }
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{ uses V{ 0 1 4 5 10 } }
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{ ranges V{ T{ live-range f 0 10 } } }
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} 5 split-before-use [ f >>split-next ] bi@
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] unit-test
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[
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T{ live-interval
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{ vreg T{ vreg { reg-class int-regs } { n 1 } } }
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@ -1858,6 +1908,8 @@ test-diamond
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[ _spill ] [ 3 get instructions>> second class ] unit-test
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[ f ] [ 3 get instructions>> [ _reload? ] any? ] unit-test
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[ _reload ] [ 4 get instructions>> first class ] unit-test
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! Resolve pass
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@ -1975,4 +2027,77 @@ V{
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[ V{ 3 2 1 } ] [ 9 get instructions>> [ _reload? ] filter [ n>> ] map ] unit-test
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! Resolve pass should insert this
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[ _reload ] [ 5 get instructions>> first class ] unit-test
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[ _reload ] [ 5 get instructions>> first class ] unit-test
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! Some random bug
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V{
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##peek f V int-regs 3 D 0 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##branch }
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} 0 test-bb
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V{ T{ ##branch } } 1 test-bb
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V{
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 3 D 3 }
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 0 D 3 }
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T{ ##branch }
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} 2 test-bb
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V{ T{ ##branch } } 3 test-bb
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V{
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T{ ##return }
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} 4 test-bb
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test-diamond
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[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
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! Spilling an interval immediately after its activated;
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! and the interval does not have a use at the activation point
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V{
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##branch }
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} 0 test-bb
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V{ T{ ##branch } } 1 test-bb
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V{
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##branch }
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} 2 test-bb
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V{
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##branch }
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} 3 test-bb
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V{ T{ ##branch } } 4 test-bb
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V{
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##return }
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} 5 test-bb
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1 get 1vector 0 get (>>successors)
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2 get 4 get V{ } 2sequence 1 get (>>successors)
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5 get 1vector 4 get (>>successors)
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3 get 1vector 2 get (>>successors)
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5 get 1vector 3 get (>>successors)
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[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
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@ -3,6 +3,7 @@ compiler.cfg.debugger compiler.cfg.instructions
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compiler.cfg.linear-scan.debugger
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compiler.cfg.linear-scan.live-intervals
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compiler.cfg.linear-scan.numbering
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compiler.cfg.linear-scan.allocation.state
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compiler.cfg.linear-scan.resolve compiler.cfg.predecessors
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compiler.cfg.registers compiler.cfg.rpo cpu.architecture kernel
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namespaces tools.test vectors ;
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@ -12,15 +13,18 @@ IN: compiler.cfg.linear-scan.resolve.tests
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{ 3 4 } V{ 1 2 } clone [ { 5 6 } 3append-here ] keep >array
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] unit-test
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H{ { int-regs 10 } { float-regs 20 } } clone spill-counts set
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H{ } clone spill-temps set
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[
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{
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T{ _copy { dst 5 } { src 4 } { class int-regs } }
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T{ _spill { src 1 } { class int-regs } { n spill-temp } }
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T{ _spill { src 1 } { class int-regs } { n 10 } }
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _reload { dst 0 } { class int-regs } { n spill-temp } }
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T{ _spill { src 1 } { class float-regs } { n spill-temp } }
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T{ _reload { dst 0 } { class int-regs } { n 10 } }
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T{ _spill { src 1 } { class float-regs } { n 20 } }
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T{ _copy { dst 1 } { src 0 } { class float-regs } }
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T{ _reload { dst 0 } { class float-regs } { n spill-temp } }
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T{ _reload { dst 0 } { class float-regs } { n 20 } }
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}
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] [
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{
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@ -34,10 +38,10 @@ IN: compiler.cfg.linear-scan.resolve.tests
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[
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{
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T{ _spill { src 2 } { class int-regs } { n spill-temp } }
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T{ _spill { src 2 } { class int-regs } { n 10 } }
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T{ _copy { dst 2 } { src 1 } { class int-regs } }
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _reload { dst 0 } { class int-regs } { n spill-temp } }
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T{ _reload { dst 0 } { class int-regs } { n 10 } }
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}
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] [
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{
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@ -49,10 +53,10 @@ IN: compiler.cfg.linear-scan.resolve.tests
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[
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{
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T{ _spill { src 0 } { class int-regs } { n spill-temp } }
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T{ _spill { src 0 } { class int-regs } { n 10 } }
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T{ _copy { dst 0 } { src 2 } { class int-regs } }
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T{ _copy { dst 2 } { src 1 } { class int-regs } }
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T{ _reload { dst 1 } { class int-regs } { n spill-temp } }
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T{ _reload { dst 1 } { class int-regs } { n 10 } }
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}
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] [
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{
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@ -113,10 +117,10 @@ IN: compiler.cfg.linear-scan.resolve.tests
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{
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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T{ _spill { src 4 } { class int-regs } { n spill-temp } }
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T{ _spill { src 4 } { class int-regs } { n 10 } }
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T{ _copy { dst 4 } { src 0 } { class int-regs } }
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T{ _copy { dst 0 } { src 3 } { class int-regs } }
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T{ _reload { dst 3 } { class int-regs } { n spill-temp } }
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T{ _reload { dst 3 } { class int-regs } { n 10 } }
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}
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] [
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{
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@ -133,10 +137,10 @@ IN: compiler.cfg.linear-scan.resolve.tests
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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T{ _copy { dst 9 } { src 1 } { class int-regs } }
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _spill { src 4 } { class int-regs } { n spill-temp } }
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T{ _spill { src 4 } { class int-regs } { n 10 } }
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T{ _copy { dst 4 } { src 0 } { class int-regs } }
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T{ _copy { dst 0 } { src 3 } { class int-regs } }
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T{ _reload { dst 3 } { class int-regs } { n spill-temp } }
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T{ _reload { dst 3 } { class int-regs } { n 10 } }
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}
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] [
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{
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@ -3,10 +3,15 @@
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USING: accessors arrays assocs classes.parser classes.tuple
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combinators combinators.short-circuit fry hashtables kernel locals
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make math math.order namespaces sequences sets words parser
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compiler.cfg.instructions compiler.cfg.linear-scan.assignment
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compiler.cfg.liveness ;
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compiler.cfg.instructions compiler.cfg.linear-scan.allocation.state
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compiler.cfg.linear-scan.assignment compiler.cfg.liveness ;
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IN: compiler.cfg.linear-scan.resolve
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SYMBOL: spill-temps
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: spill-temp ( reg-class -- n )
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spill-temps get [ next-spill-slot ] cache ;
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<<
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TUPLE: operation from to reg-class ;
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@ -116,11 +121,15 @@ ERROR: resolve-error ;
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: break-cycle-n ( operations -- operations' )
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split-cycle [
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[ from>> spill-temp <spill-slot> ]
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[ reg-class>> ] bi \ register->memory boa
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[ from>> ]
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[ reg-class>> spill-temp <spill-slot> ]
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[ reg-class>> ]
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tri \ register->memory boa
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] [
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[ to>> spill-temp <spill-slot> swap ]
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[ reg-class>> ] bi \ memory->register boa
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[ reg-class>> spill-temp <spill-slot> ]
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[ to>> ]
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[ reg-class>> ]
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tri \ memory->register boa
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] bi [ 1array ] bi@ surround ;
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: break-cycle ( operations -- operations' )
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@ -197,4 +206,5 @@ ERROR: resolve-error ;
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dup successors>> [ resolve-edge-data-flow ] with each ;
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: resolve-data-flow ( rpo -- )
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H{ } clone spill-temps set
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[ resolve-block-data-flow ] each ;
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