math.vectors.simd: add hlshift, hrshift (128-bit shift), vbitandn intrinsics
Slava Pestov
parent
2de6ab9e21
commit
b2ea3afd84
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@ -340,6 +340,21 @@ def: dst/scalar-rep
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use: src
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literal: rep ;
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PURE-INSN: ##horizontal-sub-vector
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def: dst/scalar-rep
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use: src
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literal: rep ;
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PURE-INSN: ##horizontal-shl-vector
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def: dst
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use: src1
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literal: src2 rep ;
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PURE-INSN: ##horizontal-shr-vector
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def: dst
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use: src1
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literal: src2 rep ;
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PURE-INSN: ##abs-vector
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def: dst
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use: src
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@ -355,6 +370,11 @@ def: dst
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use: src1 src2
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literal: rep ;
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PURE-INSN: ##andn-vector
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def: dst
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use: src1 src2
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literal: rep ;
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PURE-INSN: ##or-vector
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def: dst
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use: src1 src2
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@ -167,10 +167,13 @@ IN: compiler.cfg.intrinsics
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{ math.vectors.simd.intrinsics:(simd-vabs) [ [ ^^abs-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vsqrt) [ [ ^^sqrt-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vbitand) [ [ ^^and-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vbitandn) [ [ ^^andn-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vbitor) [ [ ^^or-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vbitxor) [ [ ^^xor-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vlshift) [ [ ^^shl-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-vrshift) [ [ ^^shr-vector ] emit-binary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-hlshift) [ [ ^^horizontal-shl-vector ] emit-horizontal-shift ] }
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{ math.vectors.simd.intrinsics:(simd-hrshift) [ [ ^^horizontal-shr-vector ] emit-horizontal-shift ] }
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{ math.vectors.simd.intrinsics:(simd-broadcast) [ [ ^^broadcast-vector ] emit-unary-vector-op ] }
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{ math.vectors.simd.intrinsics:(simd-gather-2) [ emit-gather-vector-2 ] }
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{ math.vectors.simd.intrinsics:(simd-gather-4) [ emit-gather-vector-4 ] }
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@ -1,6 +1,6 @@
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! Copyright (C) 2009 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: accessors byte-arrays fry cpu.architecture kernel
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USING: accessors byte-arrays fry cpu.architecture kernel math
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sequences compiler.tree.propagation.info
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compiler.cfg.builder.blocks compiler.cfg.stacks
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compiler.cfg.stacks.local compiler.cfg.hats
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@ -9,8 +9,8 @@ compiler.cfg.intrinsics.alien ;
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IN: compiler.cfg.intrinsics.simd
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: emit-vector-op ( node quot: ( rep -- ) -- )
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[ dup node-input-infos last literal>> ] dip over representation?
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[ [ drop ] 2dip call ] [ 2drop emit-primitive ] if ; inline
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[ dup node-input-infos last literal>> dup representation? ] dip
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'[ nip @ ] [ drop emit-primitive ] if ; inline
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: emit-binary-vector-op ( node quot -- )
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'[ [ ds-drop 2inputs ] dip @ ds-push ] emit-vector-op ; inline
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@ -18,6 +18,16 @@ IN: compiler.cfg.intrinsics.simd
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: emit-unary-vector-op ( node quot -- )
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'[ [ ds-drop ds-pop ] dip @ ds-push ] emit-vector-op ; inline
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: emit-horizontal-shift ( node quot -- )
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[
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dup node-input-infos
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[ second literal>> ] [ third literal>> ] bi
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2dup [ integer? ] [ representation? ] bi* and
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] dip
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'[ [ drop ds-drop ds-drop ds-pop ] 2dip @ ds-push ]
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[ 2drop emit-primitive ]
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if ; inline
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: emit-gather-vector-2 ( node -- )
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[ ^^gather-vector-2 ] emit-binary-vector-op ;
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@ -176,8 +176,12 @@ CODEGEN: ##min-vector %min-vector
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CODEGEN: ##max-vector %max-vector
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CODEGEN: ##sqrt-vector %sqrt-vector
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CODEGEN: ##horizontal-add-vector %horizontal-add-vector
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CODEGEN: ##horizontal-sub-vector %horizontal-sub-vector
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CODEGEN: ##horizontal-shl-vector %horizontal-shl-vector
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CODEGEN: ##horizontal-shr-vector %horizontal-shr-vector
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CODEGEN: ##abs-vector %abs-vector
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CODEGEN: ##and-vector %and-vector
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CODEGEN: ##andn-vector %andn-vector
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CODEGEN: ##or-vector %or-vector
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CODEGEN: ##xor-vector %xor-vector
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CODEGEN: ##shl-vector %shl-vector
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@ -17,10 +17,13 @@ IN: compiler.tree.propagation.simd
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(simd-vabs)
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(simd-vsqrt)
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(simd-vbitand)
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(simd-vbitandn)
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(simd-vbitor)
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(simd-vbitxor)
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(simd-vlshift)
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(simd-vrshift)
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(simd-hlshift)
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(simd-hrshift)
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(simd-broadcast)
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(simd-gather-2)
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(simd-gather-4)
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@ -225,12 +225,16 @@ HOOK: %min-vector cpu ( dst src1 src2 rep -- )
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HOOK: %max-vector cpu ( dst src1 src2 rep -- )
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HOOK: %sqrt-vector cpu ( dst src rep -- )
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HOOK: %horizontal-add-vector cpu ( dst src rep -- )
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HOOK: %horizontal-sub-vector cpu ( dst src rep -- )
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HOOK: %abs-vector cpu ( dst src rep -- )
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HOOK: %and-vector cpu ( dst src1 src2 rep -- )
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HOOK: %andn-vector cpu ( dst src1 src2 rep -- )
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HOOK: %or-vector cpu ( dst src1 src2 rep -- )
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HOOK: %xor-vector cpu ( dst src1 src2 rep -- )
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HOOK: %shl-vector cpu ( dst src1 src2 rep -- )
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HOOK: %shr-vector cpu ( dst src1 src2 rep -- )
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HOOK: %horizontal-shl-vector cpu ( dst src1 src2 rep -- )
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HOOK: %horizontal-shr-vector cpu ( dst src1 src2 rep -- )
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HOOK: %integer>scalar cpu ( dst src rep -- )
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HOOK: %scalar>integer cpu ( dst src rep -- )
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@ -250,12 +254,16 @@ HOOK: %min-vector-reps cpu ( -- reps )
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HOOK: %max-vector-reps cpu ( -- reps )
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HOOK: %sqrt-vector-reps cpu ( -- reps )
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HOOK: %horizontal-add-vector-reps cpu ( -- reps )
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HOOK: %horizontal-sub-vector-reps cpu ( -- reps )
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HOOK: %abs-vector-reps cpu ( -- reps )
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HOOK: %and-vector-reps cpu ( -- reps )
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HOOK: %andn-vector-reps cpu ( -- reps )
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HOOK: %or-vector-reps cpu ( -- reps )
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HOOK: %xor-vector-reps cpu ( -- reps )
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HOOK: %shl-vector-reps cpu ( -- reps )
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HOOK: %shr-vector-reps cpu ( -- reps )
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HOOK: %horizontal-shl-vector-reps cpu ( -- reps )
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HOOK: %horizontal-shr-vector-reps cpu ( -- reps )
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HOOK: %unbox-alien cpu ( dst src -- )
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HOOK: %unbox-any-c-ptr cpu ( dst src temp -- )
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@ -412,6 +412,22 @@ M: x86 %horizontal-add-vector-reps
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{ sse3? { float-4-rep double-2-rep } }
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} available-reps ;
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M: x86 %horizontal-shl-vector ( dst src1 src2 rep -- )
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two-operand PSLLDQ ;
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M: x86 %horizontal-shl-vector-reps
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{
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{ sse2? { char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
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} available-reps ;
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M: x86 %horizontal-shr-vector ( dst src1 src2 rep -- )
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two-operand PSRLDQ ;
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M: x86 %horizontal-shr-vector-reps
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{
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{ sse2? { char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
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} available-reps ;
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M: x86 %abs-vector ( dst src rep -- )
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{
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{ char-16-rep [ PABSB ] }
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@ -450,6 +466,20 @@ M: x86 %and-vector-reps
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{ sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
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} available-reps ;
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M: x86 %andn-vector ( dst src1 src2 rep -- )
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[ two-operand ] keep
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{
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{ float-4-rep [ ANDNPS ] }
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{ double-2-rep [ ANDNPD ] }
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[ drop PANDN ]
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} case ;
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M: x86 %andn-vector-reps
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{
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{ sse? { float-4-rep } }
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{ sse2? { double-2-rep char-16-rep uchar-16-rep short-8-rep ushort-8-rep int-4-rep uint-4-rep longlong-2-rep ulonglong-2-rep } }
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} available-reps ;
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M: x86 %or-vector ( dst src1 src2 rep -- )
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[ two-operand ] keep
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{
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@ -40,14 +40,18 @@ SIMD-OP: vsqrt
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SIMD-OP: sum
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SIMD-OP: vabs
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SIMD-OP: vbitand
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SIMD-OP: vbitandn
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SIMD-OP: vbitor
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SIMD-OP: vbitxor
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SIMD-OP: vlshift
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SIMD-OP: vrshift
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SIMD-OP: hlshift
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SIMD-OP: hrshift
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: (simd-broadcast) ( x rep -- v ) bad-simd-call ;
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: (simd-gather-2) ( a b rep -- v ) bad-simd-call ;
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: (simd-gather-4) ( a b c d rep -- v ) bad-simd-call ;
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: assert-positive ( x -- y ) ;
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: alien-vector ( c-ptr n rep -- value )
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@ -110,10 +114,13 @@ M: vector-rep supported-simd-op?
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{ \ (simd-sum) [ %horizontal-add-vector-reps ] }
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{ \ (simd-vabs) [ %abs-vector-reps ] }
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{ \ (simd-vbitand) [ %and-vector-reps ] }
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{ \ (simd-vbitandn) [ %andn-vector-reps ] }
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{ \ (simd-vbitor) [ %or-vector-reps ] }
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{ \ (simd-vbitxor) [ %xor-vector-reps ] }
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{ \ (simd-vlshift) [ %shl-vector-reps ] }
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{ \ (simd-vrshift) [ %shr-vector-reps ] }
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{ \ (simd-hlshift) [ %horizontal-shl-vector-reps ] }
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{ \ (simd-hrshift) [ %horizontal-shr-vector-reps ] }
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{ \ (simd-broadcast) [ %broadcast-vector-reps ] }
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{ \ (simd-gather-2) [ %gather-vector-2-reps ] }
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{ \ (simd-gather-4) [ %gather-vector-4-reps ] }
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@ -63,12 +63,12 @@ $nl
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} ;
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ARTICLE: "math.vectors.simd.words" "SIMD vector words"
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"For each SIMD vector type, several words are defined:"
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"For each SIMD vector type, several words are defined, where " { $snippet "type" } " is the type in question:"
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{ $table
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{ "Word" "Stack effect" "Description" }
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{ { $snippet "type-with" } { $snippet "( x -- simd-array )" } "creates a new instance where all components are set to a single scalar" }
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{ { $snippet "type-boa" } { $snippet "( ... -- simd-array )" } "creates a new instance where components are read from the stack" }
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{ { $snipept "type-cast" } { $snippet "( simd-array -- simd-array' )" } "creates a new SIMD array where the underlying data is taken from another SIMD array, with no format conversion" }
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{ { $snippet "type-cast" } { $snippet "( simd-array -- simd-array' )" } "creates a new SIMD array where the underlying data is taken from another SIMD array, with no format conversion" }
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{ { $snippet ">type" } { $snippet "( seq -- simd-array )" } "creates a new instance initialized with the elements of an existing sequence, which must have the correct length" }
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{ { $snippet "type{" } { $snippet "type{ elements... }" } "parsing word defining literal syntax for an SIMD vector; the correct number of elements must be given" }
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}
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@ -148,9 +148,13 @@ CONSTANT: simd-classes
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: remove-integer-words ( alist -- alist' )
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[ drop { vlshift vrshift } member? not ] assoc-filter ;
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: remove-horizontal-shifts ( alist -- alist' )
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[ drop { hlshift hrshift } member? not ] assoc-filter ;
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: ops-to-check ( elt-class -- alist )
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[ vector-words >alist ] dip
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float = [ remove-integer-words ] [ remove-float-words ] if ;
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float = [ remove-integer-words ] [ remove-float-words ] if
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remove-horizontal-shifts ;
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: check-vector-ops ( class elt-class compare-quot -- )
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[
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@ -255,3 +259,15 @@ STRUCT: simd-struct
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] unit-test
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[ ] [ char-16 new 1array stack. ] unit-test
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[ int-4{ 256 512 1024 2048 } ]
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[ int-4{ 1 2 4 8 } 1 hlshift ] unit-test
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[ int-4{ 256 512 1024 2048 } ]
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[ int-4{ 1 2 4 8 } [ { int-4 } declare 1 hlshift ] compile-call ] unit-test
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[ int-4{ 1 2 4 8 } ]
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[ int-4{ 256 512 1024 2048 } 1 hrshift ] unit-test
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[ int-4{ 1 2 4 8 } ]
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[ int-4{ 256 512 1024 2048 } [ { int-4 } declare 1 hrshift ] compile-call ] unit-test
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@ -82,10 +82,13 @@ H{
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{ vabs { +vector+ -> +vector+ } }
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{ vsqrt { +vector+ -> +vector+ } }
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{ vbitand { +vector+ +vector+ -> +vector+ } }
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{ vbitandn { +vector+ +vector+ -> +vector+ } }
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{ vbitor { +vector+ +vector+ -> +vector+ } }
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{ vbitxor { +vector+ +vector+ -> +vector+ } }
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{ vlshift { +vector+ +scalar+ -> +vector+ } }
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{ vrshift { +vector+ +scalar+ -> +vector+ } }
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{ hlshift { +vector+ +scalar+ -> +vector+ } }
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{ hrshift { +vector+ +scalar+ -> +vector+ } }
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}
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PREDICATE: vector-word < word vector-words key? ;
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@ -116,7 +119,7 @@ M: vector-word subwords specializations values [ word? ] filter ;
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:: input-signature ( word array-type elt-type -- signature )
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array-type elt-type word word-schema inputs signature-for-schema ;
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: vector-words-for-type ( elt-type -- alist )
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: vector-words-for-type ( elt-type -- words )
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{
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! Can't do shifts on floats
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{ [ dup float class<= ] [ vector-words keys { vlshift vrshift } diff ] }
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@ -125,10 +128,13 @@ M: vector-word subwords specializations values [ word? ] filter ;
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! Can't compute square root of complex numbers (vsqrt uses fsqrt not sqrt)
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{ [ dup complex class<= ] [ vector-words keys { vsqrt } diff ] }
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[ { } ]
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} cond nip ;
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} cond
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! Don't specialize horizontal shifts at all, they're only for SIMD
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{ hlshift hrshift } diff
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nip ;
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:: specialize-vector-words ( array-type elt-type simd -- )
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elt-type vector-words-for-type [
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elt-type vector-words-for-type simd keys union [
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[ array-type elt-type simd specialize-vector-word ]
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[ array-type elt-type input-signature ]
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[ ]
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@ -36,6 +36,7 @@ $nl
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{ $subsection vmin }
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"Bitwise operations:"
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{ $subsection vbitand }
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{ $subsection vbitandn }
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{ $subsection vbitor }
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{ $subsection vbitxor }
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{ $subsection vlshift }
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@ -197,6 +198,11 @@ HELP: vbitand
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{ $description "Takes the bitwise and of " { $snippet "u" } " and " { $snippet "v" } " component-wise." }
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{ $notes "Unlike " { $link bitand } ", this word may be used on a specialized array of floats or doubles, in which case the bitwise representation of the floating point numbers is operated upon." } ;
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HELP: vbitandn
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{ $values { "u" "a sequence of real numbers" } { "v" "a sequence of real numbers" } { "w" "a sequence of real numbers" } }
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{ $description "Takes the bitwise and-not of " { $snippet "u" } " and " { $snippet "v" } " component-wise, where " { $snippet "x and-not y" } " is defined as " { $snippet "not(x) and y" } "." }
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{ $notes "This word may be used on a specialized array of floats or doubles, in which case the bitwise representation of the floating point numbers is operated upon." } ;
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HELP: vbitor
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{ $values { "u" "a sequence of real numbers" } { "v" "a sequence of real numbers" } { "w" "a sequence of real numbers" } }
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{ $description "Takes the bitwise or of " { $snippet "u" } " and " { $snippet "v" } " component-wise." }
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@ -217,6 +223,14 @@ HELP: vrshift
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{ $description "Shifts each element of " { $snippet "u" } " to the right by " { $snippet "n" } " bits." }
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{ $notes "Undefined behavior will result if " { $snippet "n" } " is negative." } ;
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HELP: hlshift
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{ $values { "u" "a SIMD array" } { "n" "a non-negative integer" } { "w" "a SIMD array" } }
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{ $description "Shifts the entire SIMD array to the left by " { $snippet "n" } " bytes. This word may only be used in a context where the compiler can statically infer that the input is a SIMD array." } ;
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HELP: hrshift
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{ $values { "u" "a SIMD array" } { "n" "a non-negative integer" } { "w" "a SIMD array" } }
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{ $description "Shifts the entire SIMD array to the right by " { $snippet "n" } " bytes. This word may only be used in a context where the compiler can statically infer that the input is a SIMD array." } ;
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HELP: norm-sq
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{ $values { "v" "a sequence of numbers" } { "x" "a non-negative real number" } }
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{ $description "Computes the squared length of a mathematical vector." } ;
|
||||
|
|
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|||
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|
@ -1,7 +1,7 @@
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|||
! Copyright (C) 2005, 2009 Slava Pestov.
|
||||
! See http://factorcode.org/license.txt for BSD license.
|
||||
USING: arrays alien.c-types kernel sequences math math.functions
|
||||
hints math.order math.libm fry combinators ;
|
||||
hints math.order math.libm fry combinators byte-arrays accessors ;
|
||||
QUALIFIED-WITH: alien.c-types c
|
||||
IN: math.vectors
|
||||
|
||||
|
|
@ -62,9 +62,12 @@ PRIVATE>
|
|||
[ drop call ]
|
||||
} case ; inline
|
||||
|
||||
: bitandn ( x y -- z ) [ bitnot ] dip bitand ; inline
|
||||
|
||||
PRIVATE>
|
||||
|
||||
: vbitand ( u v -- w ) over '[ _ [ bitand ] fp-bitwise-op ] 2map ;
|
||||
: vbitandn ( u v -- w ) over '[ _ [ bitandn ] fp-bitwise-op ] 2map ;
|
||||
: vbitor ( u v -- w ) over '[ _ [ bitor ] fp-bitwise-op ] 2map ;
|
||||
: vbitxor ( u v -- w ) over '[ _ [ bitxor ] fp-bitwise-op ] 2map ;
|
||||
: vbitnot ( u -- w ) dup '[ _ [ bitnot ] fp-bitwise-unary ] map ;
|
||||
|
|
@ -86,6 +89,14 @@ PRIVATE>
|
|||
: vlshift ( u n -- w ) '[ _ shift ] map ;
|
||||
: vrshift ( u n -- w ) neg '[ _ shift ] map ;
|
||||
|
||||
: hlshift ( u n -- w )
|
||||
[ clone ] dip
|
||||
'[ _ <byte-array> append 16 tail* ] change-underlying ;
|
||||
|
||||
: hrshift ( u n -- w )
|
||||
[ clone ] dip
|
||||
'[ _ <byte-array> prepend 16 head* ] change-underlying ;
|
||||
|
||||
: vfloor ( u -- v ) [ floor ] map ;
|
||||
: vceiling ( u -- v ) [ ceiling ] map ;
|
||||
: vtruncate ( u -- v ) [ truncate ] map ;
|
||||
|
|
|
|||
Loading…
Reference in New Issue