compiler.cfg.linear-scan.resolve: More fixes
Slava Pestov
parent
da13681bc8
commit
c00af97fa1
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@ -1,7 +1,7 @@
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! Copyright (C) 2008, 2009 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: accessors kernel math assocs namespaces sequences heaps
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fry make combinators sets
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fry make combinators sets locals
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cpu.architecture
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compiler.cfg.def-use
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compiler.cfg.registers
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@ -116,8 +116,8 @@ ERROR: already-reloaded ;
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] [ 2drop ] if
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] if ;
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: prepare-insn ( insn -- )
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insn#>> [ expire-old-intervals ] [ activate-new-intervals ] bi ;
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: prepare-insn ( n -- )
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[ expire-old-intervals ] [ activate-new-intervals ] bi ;
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GENERIC: assign-registers-in-insn ( insn -- )
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@ -171,29 +171,33 @@ M: ##gc assign-registers-in-insn
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M: insn assign-registers-in-insn drop ;
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: begin-block ( bb -- )
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dup block-from prepare-insn
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[ block-from compute-live-values ] keep register-live-ins get set-at ;
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: end-block ( bb -- )
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[ block-to compute-live-values ] keep register-live-outs get set-at ;
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: vreg-at-start ( vreg bb -- state ) register-live-ins get at at ;
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ERROR: bad-vreg vreg ;
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: vreg-at-end ( vreg bb -- state ) register-live-outs get at at ;
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: vreg-at-start ( vreg bb -- state )
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register-live-ins get at ?at [ bad-vreg ] unless ;
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: assign-registers-in-block ( bb -- )
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dup
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begin-block
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[
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: vreg-at-end ( vreg bb -- state )
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register-live-outs get at ?at [ bad-vreg ] unless ;
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:: assign-registers-in-block ( bb -- )
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bb [
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[
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bb begin-block
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[
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[ prepare-insn ]
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[ insn#>> prepare-insn ]
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[ assign-registers-in-insn ]
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[ , ]
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tri
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] each
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bb end-block
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] V{ } make
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] change-instructions
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end-block ;
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] change-instructions drop ;
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: assign-registers ( live-intervals rpo -- )
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[ init-assignment ] dip
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@ -1910,4 +1910,69 @@ V{
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[ t ] [ 3 get instructions>> [ _spill? ] any? ] unit-test
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[ t ] [ 5 get instructions>> [ _reload? ] any? ] unit-test
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[ t ] [ 5 get instructions>> [ _reload? ] any? ] unit-test
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! A more complicated failure case with resolve that came up after the above
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! got fixed
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V{ T{ ##branch } } 0 test-bb
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V{
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##peek f V int-regs 1 D 1 }
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T{ ##peek f V int-regs 2 D 2 }
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T{ ##peek f V int-regs 3 D 3 }
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T{ ##peek f V int-regs 4 D 0 }
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T{ ##branch }
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} 1 test-bb
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V{ T{ ##branch } } 2 test-bb
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V{ T{ ##branch } } 3 test-bb
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V{
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 3 D 3 }
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T{ ##replace f V int-regs 4 D 4 }
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T{ ##replace f V int-regs 0 D 0 }
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T{ ##branch }
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} 4 test-bb
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V{ T{ ##replace f V int-regs 0 D 0 } T{ ##branch } } 5 test-bb
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V{ T{ ##return } } 6 test-bb
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V{ T{ ##branch } } 7 test-bb
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V{
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 3 D 3 }
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T{ ##peek f V int-regs 5 D 1 }
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T{ ##peek f V int-regs 6 D 2 }
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T{ ##peek f V int-regs 7 D 3 }
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T{ ##peek f V int-regs 8 D 4 }
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T{ ##replace f V int-regs 5 D 1 }
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T{ ##replace f V int-regs 6 D 2 }
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T{ ##replace f V int-regs 7 D 3 }
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T{ ##replace f V int-regs 8 D 4 }
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T{ ##branch }
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} 8 test-bb
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V{
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T{ ##replace f V int-regs 1 D 1 }
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T{ ##replace f V int-regs 2 D 2 }
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T{ ##replace f V int-regs 3 D 3 }
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T{ ##return }
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} 9 test-bb
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0 get 1 get 1vector >>successors drop
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1 get 2 get 7 get V{ } 2sequence >>successors drop
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7 get 8 get 1vector >>successors drop
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8 get 9 get 1vector >>successors drop
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2 get 3 get 5 get V{ } 2sequence >>successors drop
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3 get 4 get 1vector >>successors drop
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4 get 9 get 1vector >>successors drop
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5 get 6 get 1vector >>successors drop
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[ ] [ { 1 2 3 4 } test-linear-scan-on-cfg ] unit-test
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[ _spill ] [ 1 get instructions>> second class ] unit-test
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[ _reload ] [ 4 get instructions>> 4 swap nth class ] unit-test
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[ V{ 3 2 1 } ] [ 8 get instructions>> [ _spill? ] filter [ n>> ] map ] unit-test
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[ V{ 3 2 1 } ] [ 9 get instructions>> [ _reload? ] filter [ n>> ] map ] unit-test
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! Resolve pass should insert this
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[ _reload ] [ 5 get instructions>> first class ] unit-test
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