compiler.cfg.*: even more compiler docs
Björn Lindqvist
John Benediktsson
parent
997f95196c
commit
c3ca8bd859
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@ -4,7 +4,7 @@ IN: compiler.cfg.def-use
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HELP: compute-insns
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{ $values { "cfg" cfg } }
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{ $description "Computes a mapping from vregs to the instructions that define them and store the result in the " { $link insns } " variable." } ;
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{ $description "Computes a mapping from vregs to the instructions that define them and store the result in the " { $link insns } " variable. The " { $link insn-of } " word can then be used to access the assoc." } ;
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HELP: defs-vregs
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{ $values { "insn" insn } { "seq" sequence } }
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@ -1,6 +1,6 @@
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USING: alien arrays assocs classes compiler.cfg compiler.cfg.value-numbering
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compiler.codegen.gc-maps cpu.architecture help.markup help.syntax kernel
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layouts sequences slots.private system ;
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USING: alien arrays assocs classes compiler.cfg compiler.cfg.ssa.destruction
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compiler.cfg.value-numbering compiler.codegen.gc-maps cpu.architecture
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help.markup help.syntax kernel layouts sequences slots.private system ;
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IN: compiler.cfg.instructions
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HELP: ##alien-invoke
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@ -112,6 +112,13 @@ HELP: ##mul-vector
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HELP: ##no-tco
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{ $class-description "A dummy instruction that simply inhibits TCO." } ;
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HELP: ##parallel-copy
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{ $class-description "An instruction for performing multiple copies. It allows for optimizations or (or prunings) if more than one source or destination vreg is the same. They are transformed into " { $link ##copy } " instructions in " { $link destruct-ssa } ". It has the following slots:"
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{ $table
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{ { $slot "values" } { "An assoc mapping source vregs to destinations." } }
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}
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} ;
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HELP: ##peek
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{ $class-description
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"Copies a value from a stack location to a machine register."
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@ -192,7 +199,15 @@ HELP: ##store-memory-imm
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{ $class-description "Instruction that copies an 8 byte value from a XMM register to a memory location addressed by a normal register. This instruction is often turned into a cheaper " { $link ##store-memory } " instruction in the " { $link value-numbering } " pass." } ;
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HELP: ##vector>scalar
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{ $class-description "This instruction is very similar to " { $link ##copy } "." }
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{ $class-description
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"This instruction is very similar to " { $link ##copy } "."
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{ $table
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{ { $slot "dst" } { "destination vreg" } }
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{ { $slot "src" } { "source vreg" } }
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{ { $slot "rep" } { "representation for the source vreg" } }
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}
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}
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{ $notes "The two vregs must not necessarily share the same representation." }
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{ $see-also %vector>scalar } ;
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HELP: ##write-barrier
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@ -258,6 +273,7 @@ $nl
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"Instruction classes for moving values around:"
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{ $subsections
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##copy
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##parallel-copy
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##peek
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##reload
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##replace
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@ -316,7 +332,7 @@ $nl
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##load-integer
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##load-reference
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}
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"Floating point instructions:"
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"Floating point SIMD instructions:"
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{ $subsections
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##add-float
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##div-float
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@ -0,0 +1,8 @@
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USING: compiler.cfg.instructions compiler.tree help.markup help.syntax
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math.vectors ;
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IN: compiler.cfg.intrinsics.simd
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HELP: emit-simd-v+
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{ $values { "node" node } }
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{ $description "Emits instructions for SIMD vector addition." }
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{ $see-also ##add-vector v+ } ;
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@ -1,6 +1,7 @@
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USING: assocs compiler.cfg compiler.cfg.instructions
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compiler.cfg.linear-scan.live-intervals compiler.cfg.registers heaps help.markup
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help.syntax math ;
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compiler.cfg.linear-scan.live-intervals
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compiler.cfg.linear-scan.allocation.state compiler.cfg.liveness
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compiler.cfg.registers heaps help.markup help.syntax math ;
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IN: compiler.cfg.linear-scan.assignment
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HELP: add-pending
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@ -16,6 +17,10 @@ HELP: assign-gc-roots
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{ $values { "gc-map" gc-map } }
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{ $description "Assigns spill slots for all gc roots in a gc map." } ;
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HELP: assign-registers-in-block
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{ $values { "bb" basic-block } }
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{ $description "Assigns registers and also inserts " { $link ##reload } " and " { $link ##spill } " instructions." } ;
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HELP: assign-registers-in-insn
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{ $values { "insn" insn } }
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{ $description "Assigns physical registers and spill slots for the virtual registers used by the instruction." } ;
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@ -24,7 +29,7 @@ HELP: machine-edge-live-ins
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{ $var-description "Mapping from basic blocks to predecessors to values which are live on a particular incoming edge." } ;
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HELP: machine-live-ins
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{ $var-description "Mapping from basic blocks to values which are live at the start on all incoming CFG edges." } ;
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{ $var-description "Mapping from basic blocks to values which are live at the start on all incoming CFG edges. It's like " { $link live-ins } " except the registers are physical instead of virtual." } ;
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HELP: machine-live-outs
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{ $var-description "Mapping from " { $link basic-block } " to an " { $link assoc } " of pairs which are the values that are live at the end. The keys of the pairs are virtual registers and the values are either real registers or spill slots." } ;
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@ -37,10 +42,10 @@ HELP: unhandled-intervals
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{ $var-description { $link min-heap } " of live intervals which still need a register allocation." } ;
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HELP: vreg>reg
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{ $values { "vreg" "virtual register" } { "reg" "register" } }
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{ $description "If a live vreg is not in the pending set, then it must have been spilled." }
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{ $errors "Can throw a " { $link bad-vreg } " error." }
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{ $see-also pending-interval-assoc } ;
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{ $values { "vreg" "virtual register" } { "reg/spill-slot" "a register or a spill slot" } }
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{ $description "Translates a virtual register to a physical one. If the vreg is not in the pending set, then it must have been spilled and its spill slot is returned." }
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{ $errors "Can throw a " { $link bad-vreg } " error if the vreg is not in the " { $link pending-interval-assoc } " and also doesn't have a spill slot registered." }
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{ $see-also lookup-spill-slot pending-interval-assoc } ;
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HELP: vregs>regs
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{ $values { "vregs" "a sequence of virtual registers" } { "assoc" assoc } }
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@ -53,7 +58,12 @@ HELP: vreg>spill-slot
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ARTICLE: "compiler.cfg.linear-scan.assignment" "Assigning registers to live intervals"
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"The " { $vocab-link "compiler.cfg.linear-scan.assignment" } " assigns registers to live intervals." $nl
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"Pending intervals:"
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{ $subsections add-pending pending-interval-assoc remove-pending }
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{ $subsections
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activate-interval
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add-pending
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pending-interval-assoc
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remove-pending
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}
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"Vreg transformations:"
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{ $subsections vreg>reg vreg>spill-slot vregs>regs } ;
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@ -22,7 +22,7 @@ SYMBOL: pending-interval-assoc
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: remove-pending ( live-interval -- )
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vreg>> pending-interval-assoc get delete-at ;
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:: vreg>reg ( vreg -- reg )
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:: vreg>reg ( vreg -- reg/spill-slot )
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vreg leader :> leader
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leader pending-interval-assoc get at* [
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drop leader vreg rep-of lookup-spill-slot
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@ -63,14 +63,6 @@ SYMBOL: machine-live-outs
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: compute-live-out ( bb -- )
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[ live-out keys vregs>regs ] keep machine-live-outs get set-at ;
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: init-assignment ( live-intervals -- )
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[ [ start>> ] map ] keep zip >min-heap unhandled-intervals set
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<min-heap> pending-interval-heap set
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H{ } clone pending-interval-assoc set
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H{ } clone machine-live-ins set
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H{ } clone machine-edge-live-ins set
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H{ } clone machine-live-outs set ;
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: heap-pop-while ( heap quot: ( key -- ? ) -- values )
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'[ dup heap-empty? [ f f ] [ dup heap-peek @ ] if ]
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[ over heap-pop* ] produce 2nip ; inline
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@ -146,8 +138,17 @@ M: insn assign-registers-in-insn drop ;
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] each
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] V{ } make
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] change-instructions drop
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bb compute-live-out ;
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: init-assignment ( live-intervals -- )
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[ [ start>> ] map ] keep zip >min-heap unhandled-intervals set
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<min-heap> pending-interval-heap set
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H{ } clone pending-interval-assoc set
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H{ } clone machine-live-ins set
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H{ } clone machine-edge-live-ins set
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H{ } clone machine-live-outs set ;
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: assign-registers ( cfg live-intervals -- )
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init-assignment
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linearization-order [ kill-block?>> not ] filter
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@ -1,20 +1,8 @@
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USING: compiler.cfg.instructions help.markup help.syntax ;
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USING: compiler.cfg compiler.cfg.instructions
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compiler.cfg.linear-scan.allocation cpu.architecture help.markup help.syntax
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math sequences ;
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IN: compiler.cfg.linear-scan.live-intervals
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HELP: live-intervals
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{ $var-description "Mapping from vreg to " { $link live-interval-state } "." } ;
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HELP: sync-point
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{ $class-description "A location where all registers have to be spilled. It has the following slots:"
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{ $table
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{ { $slot "n" } { "Set from an instructions sequence number." } }
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}
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}
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{ $see-also insn } ;
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HELP: live-interval-state
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{ $class-description "A class encoding the \"liveness\" of a virtual register." } ;
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HELP: <live-interval>
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{ $values
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{ "vreg" "virtual register" }
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@ -22,3 +10,57 @@ HELP: <live-interval>
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{ "live-interval" live-interval-state }
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}
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{ $description "Creates a new live interval for a virtual register. Initially the range is empty." } ;
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HELP: block-from
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{ $values { "bb" basic-block } { "n" integer } }
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{ $description "The instruction number immediately preceeding this block." } ;
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HELP: finish-live-intervals
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{ $values { "live-intervals" sequence } { "seq" sequence } }
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{ $description "Since live intervals are computed in a backward order, we have to reverse some sequences, and compute the start and end." } ;
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HELP: live-interval-state
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{ $class-description "A class encoding the \"liveness\" of a virtual register. It has the following slots:"
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{ $table
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{ { $slot "vreg" } { "The vreg this live interval state is bound to." } }
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{
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{ $slot "reg" }
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{ "The allocated register, set in the " { $link allocate-registers } " step." }
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}
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{
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{ $slot "spill-to" }
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{ { $link spill-slot } " to use for spilling, if it needs to be spilled." }
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}
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{ { $slot "start" } { "Earliest insn# where the interval is live." } }
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{ { $slot "end" } { "Latest insn# where the interval is live." } }
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{
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{ $slot "ranges" }
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{ "Inclusive ranges where the live interval is live. This is because the [start,end] interval can have gaps." }
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}
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{
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{ $slot "uses" } { "sequence of references to instructions that use the register in the live interval." }
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}
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{
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{ $slot "reg-class" }
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{ "Register class of the interval, either "
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{ $link int-regs } " or " { $link float-regs } "." }
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}
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}
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}
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{ $notes "The " { $slot "uses" } " and " { $slot "ranges" } " will never be empty because then the interval would be unused." } ;
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HELP: live-intervals
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{ $var-description "Mapping from vreg to " { $link live-interval-state } "." } ;
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HELP: sync-point
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{ $class-description "A location where all registers have to be spilled. For example when garbage collection is run or an alien ffi call is invoked. Figuring out where in the " { $link cfg } " the sync points are is done in the " { $link compute-live-intervals } " step. The tuple has the following slots:"
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{ $table
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{ { $slot "n" } { "Set from an instructions sequence number." } }
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}
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}
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{ $see-also insn } ;
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HELP: sync-points
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{ $var-description "Sequence of sync points." } ;
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@ -3,9 +3,8 @@
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USING: accessors assocs binary-search combinators
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compiler.cfg.def-use compiler.cfg.instructions
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compiler.cfg.linearization compiler.cfg.liveness
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compiler.cfg.registers compiler.cfg.ssa.destruction.leaders
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cpu.architecture fry kernel locals math math.order namespaces
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sequences ;
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compiler.cfg.registers compiler.cfg.ssa.destruction.leaders cpu.architecture
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fry kernel locals math math.intervals math.order namespaces sequences ;
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IN: compiler.cfg.linear-scan.live-intervals
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TUPLE: live-range from to ;
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@ -164,7 +163,6 @@ TUPLE: sync-point n keep-dst? ;
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C: <sync-point> sync-point
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! Sequence of sync points
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SYMBOL: sync-points
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GENERIC: compute-sync-points* ( insn -- )
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@ -178,20 +176,18 @@ M: clobber-insn compute-sync-points*
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M: insn compute-sync-points* drop ;
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: compute-live-intervals-step ( bb -- )
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dup kill-block?>> [ drop ] [
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{
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[ block-from from set ]
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[ block-to to set ]
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[ handle-live-out ]
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[
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instructions>> <reversed> [
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[ compute-live-intervals* ]
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[ compute-sync-points* ]
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bi
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] each
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]
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} cleave
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] if ;
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{
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[ block-from from set ]
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[ block-to to set ]
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[ handle-live-out ]
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[
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instructions>> <reversed> [
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[ compute-live-intervals* ]
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[ compute-sync-points* ]
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bi
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] each
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]
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} cleave ;
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: init-live-intervals ( -- )
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H{ } clone live-intervals set
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@ -207,8 +203,6 @@ ERROR: bad-live-interval live-interval ;
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dup start>> -1 = [ bad-live-interval ] [ drop ] if ;
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: finish-live-intervals ( live-intervals -- seq )
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! Since live intervals are computed in a backward order, we have
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! to reverse some sequences, and compute the start and end.
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values dup [
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{
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[ [ { } like reverse! ] change-ranges drop ]
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@ -220,7 +214,8 @@ ERROR: bad-live-interval live-interval ;
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: compute-live-intervals ( cfg -- live-intervals sync-points )
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init-live-intervals
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linearization-order <reversed> [ compute-live-intervals-step ] each
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linearization-order <reversed> [ kill-block?>> not ] filter
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[ compute-live-intervals-step ] each
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live-intervals get finish-live-intervals
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sync-points get ;
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@ -6,6 +6,13 @@ HELP: base-pointers
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{ $var-description "Mapping from vregs to base pointer vregs. If the vreg doesn't have a base pointer, then it will be mapped to " { $link f } "." }
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{ $see-also lookup-base-pointer } ;
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HELP: compute-live-sets
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{ $values { "cfg" cfg } }
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{ $description "Main entry point for vocab. Pass must only be run after representation selection. In this pass " { $slot "gc-roots" } " are set." } ;
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HELP: edge-live-ins
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{ $var-description "Assoc mapping basic blocks to sequences of sets of vregs; each sequence is in correspondence with a predecessor." } ;
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HELP: fill-gc-map
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{ $values { "live-set" assoc } { "gc-map" gc-map } }
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{ $description "Assigns values to the " { $slot "gc-roots" } " and " { $slot "derived-roots" } " slots of the " { $link gc-map } ". Does nothing if the " { $link select-representations } " pass hasn't ran." } ;
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@ -32,9 +39,6 @@ HELP: lookup-base-pointer
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{ $description "Tries to figure out what the base pointer for a vreg is. Can't use cache here because of infinite recursion inside the quotation passed to cache" }
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{ $see-also base-pointers } ;
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HELP: edge-live-ins
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{ $var-description "Assoc mapping basic blocks to sequences of sets of vregs; each sequence is in correspondence with a predecessor." } ;
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ARTICLE: "compiler.cfg.liveness" "Liveness analysis"
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"Similar to http://en.wikipedia.org/wiki/Liveness_analysis, with three additions:"
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$nl
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@ -42,6 +46,9 @@ $nl
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"With SSA, it is not sufficient to have a single live-in set per block. There is also an edge-live-in set per edge, consisting of phi inputs from each predecessor."
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"Liveness analysis annotates call sites with GC maps indicating the spill slots in the stack frame that contain tagged pointers, and thus have to be visited if a GC occurs inside the call."
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{ "GC maps can contain derived pointers. A derived pointer is a pointer into the middle of a data heap object. Each derived pointer has a base pointer, to keep it up to date when objects are moved by the garbage collector. This extends live intervals and inserts new " { $link ##phi } " instructions." }
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} ;
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}
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$nl
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"Querying liveness data:"
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{ $subsections live-in live-in? live-out live-out? } ;
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ABOUT: "compiler.cfg.liveness"
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@ -13,7 +13,7 @@ HELP: parallel-copy
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HELP: parallel-copy-rep
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{ $values { "mapping" { $link assoc } " of { dst src } virtual register pairs" } { "insns" array } }
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{ $description "Creates " { $link ##copy } " instructions." } ;
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{ $description "Creates " { $link ##copy } " instructions. Representation selection must have been run previously." } ;
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ARTICLE: "compiler.cfg.parallel-copy" "Parallel copy"
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"Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency http://hal.archives-ouvertes.fr/docs/00/34/99/25/PDF/OutSSA-RR.pdf, Algorithm 1" ;
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@ -15,6 +15,9 @@ HELP: rep-of
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{ $description "Gets the representation for a virtual register. This word cannot be called before representation selection has run; use any-rep for " { $link ##copy } " instructions and so on." }
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{ $notes "Throws " { $link bad-vreg } " if the representation for the vreg isn't known." } ;
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HELP: representations
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{ $var-description "Mapping from vregs to their representations." } ;
|
||||
|
||||
HELP: set-rep-of
|
||||
{ $values { "rep" representation } { "vreg" number } }
|
||||
{ $description "Sets the representation for a virtual register." } ;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
USING: help.markup help.syntax ;
|
||||
IN: compiler.cfg.representations
|
||||
|
||||
ARTICLE: "compiler.cfg.representations" "Virtual register representation selection" "Virtual register representation selection. This is where decisions about integer tagging and float and vector boxing are made. The appropriate conversion operations inserted after a cost analysis." ;
|
||||
|
||||
ABOUT: "compiler.cfg.representations"
|
||||
|
|
@ -12,11 +12,6 @@ compiler.cfg.representations.selection
|
|||
compiler.cfg.utilities ;
|
||||
IN: compiler.cfg.representations
|
||||
|
||||
! Virtual register representation selection. This is where
|
||||
! decisions about integer tagging and float and vector boxing
|
||||
! are made. The appropriate conversion operations inserted
|
||||
! after a cost analysis.
|
||||
|
||||
: select-representations ( cfg -- )
|
||||
{
|
||||
needs-loops
|
||||
|
|
|
|||
|
|
@ -1,6 +1,11 @@
|
|||
USING: compiler.cfg.instructions help.markup help.syntax ;
|
||||
USING: compiler.cfg compiler.cfg.instructions
|
||||
compiler.cfg.ssa.destruction.private help.markup help.syntax ;
|
||||
IN: compiler.cfg.ssa.destruction
|
||||
|
||||
HELP: cleanup-cfg
|
||||
{ $values { "cfg" cfg } }
|
||||
{ $description "In this step, " { $link ##parallel-copy } " instructions are substituted with more concreete " { $link ##copy } " instructions. " { $link ##phi } " instructions are removed here." } ;
|
||||
|
||||
ARTICLE: "compiler.cfg.ssa.destruction" "SSA Destruction"
|
||||
"Because of the design of the register allocator, this pass has three peculiar properties."
|
||||
{ $list
|
||||
|
|
|
|||
|
|
@ -2,12 +2,12 @@ USING: assocs compiler.cfg help.markup help.syntax ;
|
|||
IN: compiler.cfg.stacks.finalize
|
||||
|
||||
HELP: inserting-peeks
|
||||
{ $values { "from" basic-block } { "to" basic-block } { "assoc" assoc } }
|
||||
{ $values { "from" basic-block } { "to" basic-block } { "set" assoc } }
|
||||
{ $description
|
||||
"A peek is inserted on an edge if the destination anticipates the stack location, the source does not anticipate it and it is not available from the source in a register." } ;
|
||||
|
||||
HELP: inserting-replaces
|
||||
{ $values { "from" basic-block } { "to" basic-block } { "assoc" assoc } }
|
||||
{ $values { "from" basic-block } { "to" basic-block } { "set" assoc } }
|
||||
{ $description
|
||||
"A replace is inserted on an edge if two conditions hold:"
|
||||
{ $list
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ HELP: translate-local-loc
|
|||
{ $examples
|
||||
{ $example
|
||||
"USING: compiler.cfg.stacks.local compiler.cfg.registers compiler.cfg.debugger namespaces prettyprint ;"
|
||||
"{ { 3 0 } { 0 0 } } D 7 translate-local-loc ."
|
||||
"D 7 { { 3 0 } { 0 0 } } translate-local-loc ."
|
||||
"D 4"
|
||||
}
|
||||
}
|
||||
|
|
@ -46,6 +46,7 @@ HELP: height-state>insns
|
|||
} ;
|
||||
|
||||
HELP: emit-changes
|
||||
{ $values { "replaces" sequence } { "state" sequence } }
|
||||
{ $description "Insert height and stack changes prior to the last instruction." } ;
|
||||
|
||||
HELP: inc-stack
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@ HELP: call-effect-slow>quot
|
|||
{ $description "Creates a quotation which wraps " { $link call-effect-unsafe } "." } ;
|
||||
|
||||
HELP: call-effect-unsafe?
|
||||
{ $values { "cached-effect" "an effect or +unknown+" } { "effect" effect } { "?" "a boolean" } }
|
||||
{ $description "Checks if the given effect is safe with regards to the cached one." } ;
|
||||
{ $values { "quot" quotation } { "effect" effect } { "?" "a boolean" } }
|
||||
{ $description "Checks if the given effect is safe with regards to the quotation." } ;
|
||||
|
||||
HELP: update-inline-cache
|
||||
{ $values { "word/quot" "word or quotation" } { "ic" inline-cache } }
|
||||
|
|
|
|||
Loading…
Reference in New Issue