Fix PowerPC compiler backend for recent changes
parent
eb0a28aa54
commit
c4719b7f5f
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@ -193,7 +193,7 @@ USERENV: jit-if 29
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USERENV: jit-epilog 30
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USERENV: jit-return 31
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USERENV: jit-profiling 32
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USERENV: jit-push-immediate 33
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USERENV: jit-push 33
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USERENV: jit-dip-word 34
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USERENV: jit-dip 35
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USERENV: jit-2dip-word 36
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@ -21,7 +21,7 @@ CONSTANT: rs-reg 14
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: next-save ( -- n ) stack-frame bootstrap-cell - ;
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: xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;
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: jit-conditional* ( test-quot true-quot -- )
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: jit-conditional* ( test-quot false-quot -- )
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[ '[ bootstrap-cell /i 1 + @ ] ] dip jit-conditional ; inline
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: jit-save-context ( -- )
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@ -53,14 +53,14 @@ CONSTANT: rs-reg 14
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[
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel
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3 ds-reg 4 STWU
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] jit-push-immediate jit-define
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] jit-push jit-define
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[
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jit-save-context
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4 0 swap LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel
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0 5 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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5 MTCTR
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BCTR
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0 3 LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel
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0 4 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
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4 MTLR
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BLRL
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] jit-primitive jit-define
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[ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define
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@ -235,7 +235,7 @@ CONSTANT: rs-reg 14
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[
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3 ds-reg 0 LWZ
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ds-reg dup 4 SUBI
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4 0 swap LOAD32 0 jit-parameter rc-absolute-ppc-2/2 rt-vm jit-rel
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0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
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5 3 quot-xt-offset LWZ
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]
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[ 5 MTLR BLRL ]
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@ -502,35 +502,39 @@ CONSTANT: rs-reg 14
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: jit-inline-cache-miss ( -- )
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jit-save-context
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3 6 MR
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4 0 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
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5 0 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym ;
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0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
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0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym
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5 MTLR
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BLRL ;
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[ jit-load-return-address jit-inline-cache-miss ]
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[ 5 MTLR BLRL ]
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[ 5 MTCTR BCTR ]
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[ 3 MTLR BLRL ]
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[ 3 MTCTR BCTR ]
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\ inline-cache-miss define-sub-primitive*
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[ jit-inline-cache-miss ]
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[ 5 MTLR BLRL ]
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[ 5 MTCTR BCTR ]
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[ 3 MTLR BLRL ]
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[ 3 MTCTR BCTR ]
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\ inline-cache-miss-tail define-sub-primitive*
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! Overflowing fixnum arithmetic
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:: jit-overflow ( insn func -- )
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jit-save-context
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3 ds-reg 0 LWZ
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4 ds-reg -4 LWZ
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3 ds-reg -4 LWZ
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4 ds-reg 0 LWZ
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ds-reg ds-reg 4 SUBI
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0 0 LI
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0 MTXER
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6 3 4 insn call( d a s -- )
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6 4 3 insn call( d a s -- )
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6 ds-reg 0 STW
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[ BNO ]
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[
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0 5 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
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0 6 LOAD32 func f rc-absolute-ppc-2/2 jit-dlsym
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6 MTLR
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BLRL
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]
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jit-conditional ;
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jit-conditional* ;
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[ [ ADDO. ] "overflow_fixnum_add" jit-overflow ] \ fixnum+ define-sub-primitive
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@ -554,7 +558,7 @@ CONSTANT: rs-reg 14
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6 MTLR
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BLRL
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]
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jit-conditional
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jit-conditional*
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] \ fixnum* define-sub-primitive
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[ "bootstrap.ppc" forget-vocab ] with-compilation-unit
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@ -28,7 +28,7 @@ big-endian off
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ds-reg bootstrap-cell ADD
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! store literal on datastack
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ds-reg [] temp0 MOV
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] jit-push-immediate jit-define
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] jit-push jit-define
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[
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temp3 0 MOV rc-absolute-cell rt-here jit-rel
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