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Fix PowerPC compiler backend for recent changes

db4
Slava Pestov 2009-12-15 09:51:20 -05:00
parent eb0a28aa54
commit c4719b7f5f
3 changed files with 24 additions and 20 deletions
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2
basis/bootstrap/image/image.factor
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@ -193,7 +193,7 @@ USERENV: jit-if 29
USERENV: jit-epilog 30 USERENV: jit-epilog 30
USERENV: jit-return 31 USERENV: jit-return 31
USERENV: jit-profiling 32 USERENV: jit-profiling 32
USERENV: jit-push-immediate 33 USERENV: jit-push 33
USERENV: jit-dip-word 34 USERENV: jit-dip-word 34
USERENV: jit-dip 35 USERENV: jit-dip 35
USERENV: jit-2dip-word 36 USERENV: jit-2dip-word 36

40
basis/cpu/ppc/bootstrap.factor
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@ -21,7 +21,7 @@ CONSTANT: rs-reg 14
: next-save ( -- n ) stack-frame bootstrap-cell - ; : next-save ( -- n ) stack-frame bootstrap-cell - ;
: xt-save ( -- n ) stack-frame 2 bootstrap-cells - ; : xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;
: jit-conditional* ( test-quot true-quot -- ) : jit-conditional* ( test-quot false-quot -- )
[ '[ bootstrap-cell /i 1 + @ ] ] dip jit-conditional ; inline [ '[ bootstrap-cell /i 1 + @ ] ] dip jit-conditional ; inline
: jit-save-context ( -- ) : jit-save-context ( -- )
@ -53,14 +53,14 @@ CONSTANT: rs-reg 14
[ [
0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel 0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel
3 ds-reg 4 STWU 3 ds-reg 4 STWU
] jit-push-immediate jit-define ] jit-push jit-define
[ [
jit-save-context jit-save-context
4 0 swap LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel 0 3 LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel
0 5 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel 0 4 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
5 MTCTR 4 MTLR
BCTR BLRL
] jit-primitive jit-define ] jit-primitive jit-define
[ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define [ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define
@ -235,7 +235,7 @@ CONSTANT: rs-reg 14
[ [
3 ds-reg 0 LWZ 3 ds-reg 0 LWZ
ds-reg dup 4 SUBI ds-reg dup 4 SUBI
4 0 swap LOAD32 0 jit-parameter rc-absolute-ppc-2/2 rt-vm jit-rel 0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
5 3 quot-xt-offset LWZ 5 3 quot-xt-offset LWZ
] ]
[ 5 MTLR BLRL ] [ 5 MTLR BLRL ]
@ -502,35 +502,39 @@ CONSTANT: rs-reg 14
: jit-inline-cache-miss ( -- ) : jit-inline-cache-miss ( -- )
jit-save-context jit-save-context
3 6 MR 3 6 MR
4 0 LOAD32 0 rc-absolute-ppc-2/2 jit-vm 0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
5 0 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym ; 0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym
5 MTLR
BLRL ;
[ jit-load-return-address jit-inline-cache-miss ] [ jit-load-return-address jit-inline-cache-miss ]
[ 5 MTLR BLRL ] [ 3 MTLR BLRL ]
[ 5 MTCTR BCTR ] [ 3 MTCTR BCTR ]
\ inline-cache-miss define-sub-primitive* \ inline-cache-miss define-sub-primitive*
[ jit-inline-cache-miss ] [ jit-inline-cache-miss ]
[ 5 MTLR BLRL ] [ 3 MTLR BLRL ]
[ 5 MTCTR BCTR ] [ 3 MTCTR BCTR ]
\ inline-cache-miss-tail define-sub-primitive* \ inline-cache-miss-tail define-sub-primitive*
! Overflowing fixnum arithmetic ! Overflowing fixnum arithmetic
:: jit-overflow ( insn func -- ) :: jit-overflow ( insn func -- )
jit-save-context jit-save-context
3 ds-reg 0 LWZ 3 ds-reg -4 LWZ
4 ds-reg -4 LWZ 4 ds-reg 0 LWZ
ds-reg ds-reg 4 SUBI ds-reg ds-reg 4 SUBI
0 0 LI 0 0 LI
0 MTXER 0 MTXER
6 3 4 insn call( d a s -- ) 6 4 3 insn call( d a s -- )
6 ds-reg 0 STW 6 ds-reg 0 STW
[ BNO ] [ BNO ]
[ [
0 5 LOAD32 0 rc-absolute-ppc-2/2 jit-vm 0 5 LOAD32 0 rc-absolute-ppc-2/2 jit-vm
0 6 LOAD32 func f rc-absolute-ppc-2/2 jit-dlsym 0 6 LOAD32 func f rc-absolute-ppc-2/2 jit-dlsym
6 MTLR
BLRL
] ]
jit-conditional ; jit-conditional* ;
[ [ ADDO. ] "overflow_fixnum_add" jit-overflow ] \ fixnum+ define-sub-primitive [ [ ADDO. ] "overflow_fixnum_add" jit-overflow ] \ fixnum+ define-sub-primitive
@ -554,7 +558,7 @@ CONSTANT: rs-reg 14
6 MTLR 6 MTLR
BLRL BLRL
] ]
jit-conditional jit-conditional*
] \ fixnum* define-sub-primitive ] \ fixnum* define-sub-primitive
[ "bootstrap.ppc" forget-vocab ] with-compilation-unit [ "bootstrap.ppc" forget-vocab ] with-compilation-unit

2
basis/cpu/x86/bootstrap.factor
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@ -28,7 +28,7 @@ big-endian off
ds-reg bootstrap-cell ADD ds-reg bootstrap-cell ADD
! store literal on datastack ! store literal on datastack
ds-reg [] temp0 MOV ds-reg [] temp0 MOV
] jit-push-immediate jit-define ] jit-push jit-define
[ [
temp3 0 MOV rc-absolute-cell rt-here jit-rel temp3 0 MOV rc-absolute-cell rt-here jit-rel