diff --git a/basis/cpu/ppc/assembler/assembler.factor b/basis/cpu/ppc/assembler/assembler.factor index dd633f4e9a..210d458605 100644 --- a/basis/cpu/ppc/assembler/assembler.factor +++ b/basis/cpu/ppc/assembler/assembler.factor @@ -209,3 +209,210 @@ MTSPR: CTR 9 r r n HEX: ffff bitand ORI ; : immediate? ( n -- ? ) HEX: -8000 HEX: 7fff between? ; : LOAD ( n r -- ) over immediate? [ LI ] [ LOAD32 ] if ; + +! Altivec/VMX instructions +VA: VMHADDSHS 32 4 +VA: VMHRADDSHS 33 4 +VA: VMLADDUHM 34 4 +VA: VMSUMUBM 36 4 +VA: VMSUMMBM 37 4 +VA: VMSUMUHM 38 4 +VA: VMSUMUHS 39 4 +VA: VMSUMSHM 40 4 +VA: VMSUMSHS 41 4 +VA: VSEL 42 4 +VA: VPERM 43 4 +VA: VSLDOI 44 4 +VA: VMADDFP 46 4 +VA: VNMSUBFP 47 4 + +VX: VADDUBM 0 4 +VX: VADDUHM 64 4 +VX: VADDUWM 128 4 +VX: VADDCUW 384 4 +VX: VADDUBS 512 4 +VX: VADDUHS 576 4 +VX: VADDUWS 640 4 +VX: VADDSBS 768 4 +VX: VADDSHS 832 4 +VX: VADDSWS 896 4 + +VX: VSUBUBM 1024 4 +VX: VSUBUHM 1088 4 +VX: VSUBUWM 1152 4 +VX: VSUBCUW 1408 4 +VX: VSUBUBS 1536 4 +VX: VSUBUHS 1600 4 +VX: VSUBUWS 1664 4 +VX: VSUBSBS 1792 4 +VX: VSUBSHS 1856 4 +VX: VSUBSWS 1920 4 + +VX: VMAXUB 2 4 +VX: VMAXUH 66 4 +VX: VMAXUW 130 4 +VX: VMAXSB 258 4 +VX: VMAXSH 322 4 +VX: VMAXSW 386 4 + +VX: VMINUB 514 4 +VX: VMINUH 578 4 +VX: VMINUW 642 4 +VX: VMINSB 770 4 +VX: VMINSH 834 4 +VX: VMINSW 898 4 + +VX: VAVGUB 1026 4 +VX: VAVGUH 1090 4 +VX: VAVGUW 1154 4 +VX: VAVGSB 1282 4 +VX: VAVGSH 1346 4 +VX: VAVGSW 1410 4 + +VX: VRLB 4 4 +VX: VRLH 68 4 +VX: VRLW 132 4 +VX: VSLB 260 4 +VX: VSLH 324 4 +VX: VSLW 388 4 +VX: VSL 452 4 +VX: VSRB 516 4 +VX: VSRH 580 4 +VX: VSRW 644 4 +VX: VSR 708 4 +VX: VSRAB 772 4 +VX: VSRAH 836 4 +VX: VSRAW 900 4 + +VX: VAND 1028 4 +VX: VANDC 1092 4 +VX: VOR 1156 4 +VX: VNOR 1284 4 +VX: VXOR 1220 4 + +VXD: MFVSCR 1540 4 +VXB: MTVSCR 1604 4 + +VX: VMULOUB 8 4 +VX: VMULOUH 72 4 +VX: VMULOSB 264 4 +VX: VMULOSH 328 4 +VX: VMULEUB 520 4 +VX: VMULEUH 584 4 +VX: VMULESB 776 4 +VX: VMULESH 840 4 +VX: VSUM4UBS 1544 4 +VX: VSUM4SBS 1800 4 +VX: VSUM4SHS 1608 4 +VX: VSUM2SWS 1672 4 +VX: VSUMSWS 1928 4 + +VX: VADDFP 10 4 +VX: VSUBFP 74 4 + +VXDB: VREFP 266 4 +VXDB: VRSQRTEFP 330 4 +VXDB: VEXPTEFP 394 4 +VXDB: VLOGEFP 458 4 +VXDB: VRFIN 522 4 +VXDB: VRFIZ 586 4 +VXDB: VRFIP 650 4 +VXDB: VRFIM 714 4 + +VX: VCFUX 778 4 +VX: VCFSX 842 4 +VX: VCTUXS 906 4 +VX: VCTSXS 970 4 + +VX: VMAXFP 1034 4 +VX: VMINFP 1098 4 + +VX: VMRGHB 12 4 +VX: VMRGHH 76 4 +VX: VMRGHW 140 4 +VX: VMRGLB 268 4 +VX: VMRGLH 332 4 +VX: VMRGLW 396 4 + +VX: VSPLTB 524 4 +VX: VSPLTH 588 4 +VX: VSPLTW 652 4 + +VXA: VSPLTISB 780 4 +VXA: VSPLTISH 844 4 +VXA: VSPLTISW 908 4 + +VX: VSLO 1036 4 +VX: VSRO 1100 4 + +VX: VPKUHUM 14 4 +VX: VPKUWUM 78 4 +VX: VPKUHUS 142 4 +VX: VPKUWUS 206 4 +VX: VPKSHUS 270 4 +VX: VPKSWUS 334 4 +VX: VPKSHSS 398 4 +VX: VPKSWSS 462 4 +VX: VPKPX 782 4 + +VXDB: VUPKHSB 526 4 +VXDB: VUPKHSH 590 4 +VXDB: VUPKLSB 654 4 +VXDB: VUPKLSH 718 4 +VXDB: VUPKHPX 846 4 +VXDB: VUPKLPX 974 4 + +: -T ( strm a b -- strm-t a b ) [ 16 bitor ] 2dip ; + +XD: DST 0 342 31 +: DSTT ( strm a b -- ) -T DST ; + +XD: DSTST 0 374 31 +: DSTSTT ( strm a b -- ) -T DSTST ; + +XD: (DSS) 0 822 31 +: DSS ( strm -- ) 0 0 (DSS) ; +: DSSALL ( -- ) 16 0 0 (DSS) ; + +XD: LVEBX 0 7 31 +XD: LVEHX 0 39 31 +XD: LVEWX 0 71 31 +XD: LVSL 0 6 31 +XD: LVSR 0 38 31 +XD: LVX 0 103 31 +XD: LVXL 0 359 31 + +XD: STVEBX 0 135 31 +XD: STVEHX 0 167 31 +XD: STVEWX 0 199 31 +XD: STVX 0 231 31 +XD: STVXL 0 487 31 + +VXR: VCMPBFP 0 966 4 +VXR: VCMPEQFP 0 198 4 +VXR: VCMPEQUB 0 6 4 +VXR: VCMPEQUH 0 70 4 +VXR: VCMPEQUW 0 134 4 +VXR: VCMPGEFP 0 454 4 +VXR: VCMPGTFP 0 710 4 +VXR: VCMPGTSB 0 774 4 +VXR: VCMPGTSH 0 838 4 +VXR: VCMPGTSW 0 902 4 +VXR: VCMPGTUB 0 518 4 +VXR: VCMPGTUH 0 582 4 +VXR: VCMPGTUW 0 646 4 + +VXR: VCMPBFP. 1 966 4 +VXR: VCMPEQFP. 1 198 4 +VXR: VCMPEQUB. 1 6 4 +VXR: VCMPEQUH. 1 70 4 +VXR: VCMPEQUW. 1 134 4 +VXR: VCMPGEFP. 1 454 4 +VXR: VCMPGTFP. 1 710 4 +VXR: VCMPGTSB. 1 774 4 +VXR: VCMPGTSH. 1 838 4 +VXR: VCMPGTSW. 1 902 4 +VXR: VCMPGTUB. 1 518 4 +VXR: VCMPGTUH. 1 582 4 +VXR: VCMPGTUW. 1 646 4 + diff --git a/basis/cpu/ppc/assembler/backend/backend.factor b/basis/cpu/ppc/assembler/backend/backend.factor index 1e6365b1e7..47222a89fe 100644 --- a/basis/cpu/ppc/assembler/backend/backend.factor +++ b/basis/cpu/ppc/assembler/backend/backend.factor @@ -36,10 +36,17 @@ SYNTAX: SD: CREATE scan-word define-sd-insn ; : x-insn ( a s b rc xo opcode -- ) [ { 1 0 11 21 16 } bitfield ] dip insn ; +: xd-insn ( d a b rc xo opcode -- ) + [ { 1 0 11 16 21 } bitfield ] dip insn ; + : (X) ( -- word quot ) CREATE scan-word scan-word scan-word [ x-insn ] 3curry ; -SYNTAX: X: (X) (( a s b -- )) define-declared ; +: (XD) ( -- word quot ) + CREATE scan-word scan-word scan-word [ xd-insn ] 3curry ; + +SYNTAX: X: (X) (( a s b -- )) define-declared ; +SYNTAX: XD: (XD) (( d a b -- )) define-declared ; : (1) ( quot -- quot' ) [ 0 ] prepose ; @@ -67,9 +74,9 @@ SYNTAX: MTSPR: CREATE scan-word scan-word scan-word scan-word [ xo-insn ] 2curry 2curry ; -SYNTAX: XO: (XO) (( a s b -- )) define-declared ; +SYNTAX: XO: (XO) (( d a b -- )) define-declared ; -SYNTAX: XO1: (XO) (1) (( a s -- )) define-declared ; +SYNTAX: XO1: (XO) (1) (( d a -- )) define-declared ; GENERIC# (B) 2 ( dest aa lk -- ) M: integer (B) 18 i-insn ; @@ -86,3 +93,40 @@ SYNTAX: BC: SYNTAX: B: CREATE-B scan-word scan-word scan-word scan-word scan-word '[ _ _ _ _ _ b-insn ] (( bo -- )) define-declared ; + +: va-insn ( d a b c xo opcode -- ) + [ { 0 6 11 16 21 } bitfield ] dip insn ; + +: (VA) ( -- word quot ) + CREATE scan-word scan-word [ va-insn ] 2curry ; + +SYNTAX: VA: (VA) (( d a b c -- )) define-declared ; + +: vx-insn ( d a b xo opcode -- ) + [ { 0 11 16 21 } bitfield ] dip insn ; + +: (VX) ( -- word quot ) + CREATE scan-word scan-word [ vx-insn ] 2curry ; +: (VXD) ( -- word quot ) + CREATE scan-word scan-word '[ 0 0 _ _ vx-insn ] ; +: (VXA) ( -- word quot ) + CREATE scan-word scan-word '[ [ 0 ] dip 0 _ _ vx-insn ] ; +: (VXB) ( -- word quot ) + CREATE scan-word scan-word '[ [ 0 0 ] dip _ _ vx-insn ] ; +: (VXDB) ( -- word quot ) + CREATE scan-word scan-word '[ [ 0 ] dip _ _ vx-insn ] ; + +SYNTAX: VX: (VX) (( d a b -- )) define-declared ; +SYNTAX: VXD: (VXD) (( d -- )) define-declared ; +SYNTAX: VXA: (VXA) (( a -- )) define-declared ; +SYNTAX: VXB: (VXB) (( b -- )) define-declared ; +SYNTAX: VXDB: (VXDB) (( d b -- )) define-declared ; + +: vxr-insn ( d a b rc xo opcode -- ) + [ { 0 10 11 16 21 } bitfield ] dip insn ; + +: (VXR) ( -- word quot ) + CREATE scan-word scan-word scan-word [ vxr-insn ] 3curry ; + +SYNTAX: VXR: (VXR) (( d a b -- )) define-declared ; +