From d5a25f99bf41702274a5cfea40a77b248f589ff1 Mon Sep 17 00:00:00 2001 From: Slava Pestov Date: Sat, 6 Feb 2010 18:41:58 +1300 Subject: [PATCH] cpu.x86.64: inline cache miss blocks have a prolog generated in the middle of a procedure; undo a recent change to non-optimizing backend to fix random crashes --- basis/cpu/x86/64/bootstrap.factor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/basis/cpu/x86/64/bootstrap.factor b/basis/cpu/x86/64/bootstrap.factor index 48b5dfd65d..bc560580fa 100644 --- a/basis/cpu/x86/64/bootstrap.factor +++ b/basis/cpu/x86/64/bootstrap.factor @@ -28,7 +28,7 @@ IN: bootstrap.x86 [ ! load entry point - safe-reg -7 [] LEA + safe-reg 0 MOV rc-absolute-cell rt-this jit-rel ! save stack frame size stack-frame-size PUSH ! push entry point