cpu.x86.64: eliminate useless instruction from primitive call sequence for a marginal to non-existent gain
parent
0569f08ea2
commit
ef53e6ecd5
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@ -63,12 +63,13 @@ IN: bootstrap.x86
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rs-reg ctx-reg context-retainstack-offset [+] MOV ;
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rs-reg ctx-reg context-retainstack-offset [+] MOV ;
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[
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[
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! ctx-reg is preserved across the call because it is non-volatile
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! in the C ABI
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jit-load-vm
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jit-load-vm
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jit-save-context
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jit-save-context
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! call the primitive
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! call the primitive
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ESP [] vm-reg MOV
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ESP [] vm-reg MOV
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0 CALL rc-relative rt-dlsym jit-rel
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0 CALL rc-relative rt-dlsym jit-rel
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! restore ds, rs registers
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jit-restore-context
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jit-restore-context
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] jit-primitive jit-define
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] jit-primitive jit-define
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@ -57,11 +57,12 @@ IN: bootstrap.x86
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ctx-reg context-retainstack-offset [+] rs-reg MOV ;
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ctx-reg context-retainstack-offset [+] rs-reg MOV ;
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: jit-restore-context ( -- )
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: jit-restore-context ( -- )
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jit-load-context
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ds-reg ctx-reg context-datastack-offset [+] MOV
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ds-reg ctx-reg context-datastack-offset [+] MOV
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rs-reg ctx-reg context-retainstack-offset [+] MOV ;
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rs-reg ctx-reg context-retainstack-offset [+] MOV ;
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[
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[
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! ctx-reg is preserved across the call because it is non-volatile
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! in the C ABI
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jit-save-context
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jit-save-context
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! call the primitive
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! call the primitive
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arg1 vm-reg MOV
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arg1 vm-reg MOV
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@ -80,6 +81,7 @@ IN: bootstrap.x86
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arg1 vm-reg MOV
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arg1 vm-reg MOV
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"begin_callback" jit-call
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"begin_callback" jit-call
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jit-load-context
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jit-restore-context
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jit-restore-context
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! call the quotation
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! call the quotation
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@ -115,6 +117,7 @@ IN: bootstrap.x86
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vm-reg 0 MOV 0 rc-absolute-cell jit-vm
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vm-reg 0 MOV 0 rc-absolute-cell jit-vm
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! Load ds and rs registers
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! Load ds and rs registers
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jit-load-context
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jit-restore-context
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jit-restore-context
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! Call quotation
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! Call quotation
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@ -168,6 +171,7 @@ IN: bootstrap.x86
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arg1 RBX MOV
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arg1 RBX MOV
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arg2 vm-reg MOV
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arg2 vm-reg MOV
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"inline_cache_miss" jit-call
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"inline_cache_miss" jit-call
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jit-load-context
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jit-restore-context ;
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jit-restore-context ;
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[ jit-load-return-address jit-inline-cache-miss ]
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[ jit-load-return-address jit-inline-cache-miss ]
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