From f8e475485a9f6b653032b7d90c87d634115b1928 Mon Sep 17 00:00:00 2001
From: Slava Pestov <slava@factorcode.org>
Date: Wed, 14 Sep 2011 01:08:32 -0700
Subject: [PATCH] Add RT_INLINE_CACHE_MISS relocation type to avoid frequent
 dlsym lookups when compiling PICs. Fixes #123

---
 basis/compiler/codegen/relocation/relocation.factor | 3 +++
 basis/compiler/constants/constants.factor           | 1 +
 basis/cpu/x86/32/bootstrap.factor                   | 2 +-
 basis/cpu/x86/64/bootstrap.factor                   | 3 ++-
 vm/code_blocks.cpp                                  | 3 +++
 vm/instruction_operands.hpp                         | 4 ++++
 6 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/basis/compiler/codegen/relocation/relocation.factor b/basis/compiler/codegen/relocation/relocation.factor
index e5132a7509..f2bc0d0de7 100644
--- a/basis/compiler/codegen/relocation/relocation.factor
+++ b/basis/compiler/codegen/relocation/relocation.factor
@@ -99,6 +99,9 @@ MEMO: cached-string>symbol ( symbol -- obj ) string>symbol ;
 : rel-exception-handler ( class -- )
     rt-exception-handler add-relocation ;
 
+: rel-inline-cache-miss ( class -- )
+    rt-inline-cache-miss add-relocation ;
+
 : init-relocation ( -- )
     V{ } clone parameter-table set
     V{ } clone literal-table set
diff --git a/basis/compiler/constants/constants.factor b/basis/compiler/constants/constants.factor
index 97da3b7516..3440b85a80 100644
--- a/basis/compiler/constants/constants.factor
+++ b/basis/compiler/constants/constants.factor
@@ -69,6 +69,7 @@ CONSTANT: rt-cards-offset 10
 CONSTANT: rt-decks-offset 11
 CONSTANT: rt-exception-handler 12
 CONSTANT: rt-dlsym-toc 13
+CONSTANT: rt-inline-cache-miss 14
 
 : rc-absolute? ( n -- ? )
     ${
diff --git a/basis/cpu/x86/32/bootstrap.factor b/basis/cpu/x86/32/bootstrap.factor
index 4474e402fe..39f72de2b9 100755
--- a/basis/cpu/x86/32/bootstrap.factor
+++ b/basis/cpu/x86/32/bootstrap.factor
@@ -192,7 +192,7 @@ IN: bootstrap.x86
     jit-save-context
     ESP 4 [+] vm-reg MOV
     ESP [] pic-tail-reg MOV
-    "inline_cache_miss" jit-call
+    0 CALL rc-relative rel-inline-cache-miss
     jit-restore-context ;
 
 [ jit-load-return-address jit-inline-cache-miss ]
diff --git a/basis/cpu/x86/64/bootstrap.factor b/basis/cpu/x86/64/bootstrap.factor
index 7e6e937f9c..162ed5125a 100755
--- a/basis/cpu/x86/64/bootstrap.factor
+++ b/basis/cpu/x86/64/bootstrap.factor
@@ -181,7 +181,8 @@ IN: bootstrap.x86
     jit-save-context
     arg1 RBX MOV
     arg2 vm-reg MOV
-    "inline_cache_miss" jit-call
+    RAX 0 MOV rc-absolute-cell rel-inline-cache-miss
+    RAX CALL
     jit-load-context
     jit-restore-context ;
 
diff --git a/vm/code_blocks.cpp b/vm/code_blocks.cpp
index 13a80849cf..d46a4a9c2c 100755
--- a/vm/code_blocks.cpp
+++ b/vm/code_blocks.cpp
@@ -269,6 +269,9 @@ void factor_vm::store_external_address(instruction_operand op)
 		op.store_value(compute_dlsym_toc_address(parameters,index));
 		break;
 #endif
+	case RT_INLINE_CACHE_MISS:
+		op.store_value((cell)&factor::inline_cache_miss);
+		break;
 	default:
 		critical_error("Bad rel type in store_external_address()",op.rel_type());
 		break;
diff --git a/vm/instruction_operands.hpp b/vm/instruction_operands.hpp
index a5286d5324..b5a9931b81 100644
--- a/vm/instruction_operands.hpp
+++ b/vm/instruction_operands.hpp
@@ -32,6 +32,9 @@ enum relocation_type {
 	RT_EXCEPTION_HANDLER,
 	/* arg is a literal table index, holding a pair (symbol/dll) */
 	RT_DLSYM_TOC,
+	/* address of inline_cache_miss function. This is a separate
+	relocation to reduce compile time and size for PICs. */
+	RT_INLINE_CACHE_MISS
 };
 
 enum relocation_class {
@@ -117,6 +120,7 @@ struct relocation_entry {
 		case RT_CARDS_OFFSET:
 		case RT_DECKS_OFFSET:
 		case RT_EXCEPTION_HANDLER:
+		case RT_INLINE_CACHE_MISS:
 			return 0;
 		default:
 			critical_error("Bad rel type in number_of_parameters()",rel_type());