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compiler.cfg.linear-scan.live-intervals: the reg-class slot can be 

removed

it's always the same as vreg>> rep-of reg-class-of so no need to store
that data twice
db4
Björn Lindqvist 2015-09-14 18:49:18 +02:00
parent 68c6654763
commit fb45bc278f
9 changed files with 37 additions and 81 deletions
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8
basis/compiler/cfg/linear-scan/allocation/allocation-tests.factor
View File

@ -1,8 +1,8 @@
USING: accessors compiler.cfg compiler.cfg.linear-scan.allocation
compiler.cfg.linear-scan.allocation.state
compiler.cfg.linear-scan.live-intervals compiler.cfg.linear-scan.ranges
cpu.architecture cpu.x86.assembler.operands heaps kernel namespaces system
tools.test ;
compiler.cfg.registers cpu.architecture cpu.x86.assembler.operands heaps kernel
namespaces system tools.test ;
IN: compiler.cfg.linear-scan.allocation.tests
: interval-[30,46] ( -- live-interval )
@ -16,20 +16,19 @@ IN: compiler.cfg.linear-scan.allocation.tests
T{ vreg-use { n 46 } { use-rep double-rep } }
}
}
{ reg-class int-regs }
} clone ;
: interval-[30,60] ( -- live-interval )
T{ live-interval-state
{ vreg 25 }
{ start 30 } { end 60 }
{ reg-class int-regs }
{ reg RAX }
} ;
cpu x86.64? [
! assign-registers
{ RAX } [
H{ { 49 int-rep } } representations set
f machine-registers init-allocator
interval-[30,46] dup machine-registers assign-register reg>>
] unit-test
@ -42,6 +41,7 @@ cpu x86.64? [
{ { RBX 1/0. } } [
f machine-registers init-allocator
H{ { 25 int-rep } { 49 int-rep } } representations set
interval-[30,60] add-active
interval-[30,46] machine-registers register-status
] unit-test

2
basis/compiler/cfg/linear-scan/allocation/allocation.factor
View File

@ -21,7 +21,7 @@ IN: compiler.cfg.linear-scan.allocation
of [ 1/0. 2array ] map ;
: register-status ( new registers -- free-pos )
over reg-class>> free-positions [
over interval-reg-class free-positions [
[ inactive-positions ] [ active-positions ] 2bi
] keep alist-max ;

21
basis/compiler/cfg/linear-scan/allocation/state/state-tests.factor
View File

@ -1,17 +1,18 @@
USING: accessors assocs combinators.extras compiler.cfg
compiler.cfg.instructions compiler.cfg.linear-scan.allocation
compiler.cfg.linear-scan.allocation.state
compiler.cfg.linear-scan.live-intervals compiler.cfg.utilities
cpu.architecture cpu.x86.assembler.operands heaps kernel layouts
literals namespaces sequences system tools.test ;
compiler.cfg.linear-scan.live-intervals compiler.cfg.registers
compiler.cfg.utilities cpu.architecture cpu.x86.assembler.operands heaps
kernel layouts literals namespaces sequences system tools.test ;
IN: compiler.cfg.linear-scan.allocation.state.tests
! active-intervals-for
{
V{ T{ live-interval-state { reg-class int-regs } { vreg 123 } } }
V{ T{ live-interval-state { vreg 123 } } }
} [
f machine-registers init-allocator
T{ live-interval-state { reg-class int-regs } { vreg 123 } }
H{ { 123 int-rep } } representations set
T{ live-interval-state { vreg 123 } }
[ add-active ] keep active-intervals-for
] unit-test
@ -23,7 +24,6 @@ IN: compiler.cfg.linear-scan.allocation.state.tests
V{
T{ live-interval-state
{ vreg 123 }
{ reg-class int-regs }
}
}
}
@ -31,7 +31,8 @@ IN: compiler.cfg.linear-scan.allocation.state.tests
}
} [
f machine-registers init-allocator
T{ live-interval-state { reg-class int-regs } { vreg 123 } } add-active
H{ { 123 int-rep } } representations set
T{ live-interval-state { vreg 123 } } add-active
active-intervals get
] unit-test
@ -99,7 +100,6 @@ ${
40 progress set
T{ live-interval-state
{ end 34 }
{ reg-class int-regs }
{ vreg 123 }
}
check-handled
@ -113,10 +113,11 @@ ${ cell } [
! inactive-intervals-for
{
V{ T{ live-interval-state { reg-class int-regs } { vreg 123 } } }
V{ T{ live-interval-state { vreg 123 } } }
} [
f machine-registers init-allocator
T{ live-interval-state { reg-class int-regs } { vreg 123 } }
H{ { 123 int-rep } } representations set
T{ live-interval-state { vreg 123 } }
[ add-inactive ] keep inactive-intervals-for
] unit-test

4
basis/compiler/cfg/linear-scan/allocation/state/state.factor
View File

@ -32,7 +32,7 @@ SYMBOL: registers
SYMBOL: active-intervals
: active-intervals-for ( live-interval -- seq )
reg-class>> active-intervals get at ;
interval-reg-class active-intervals get at ;
: add-active ( live-interval -- )
dup active-intervals-for push ;
@ -46,7 +46,7 @@ SYMBOL: active-intervals
SYMBOL: inactive-intervals
: inactive-intervals-for ( live-interval -- seq )
reg-class>> inactive-intervals get at ;
interval-reg-class inactive-intervals get at ;
: add-inactive ( live-interval -- )
dup inactive-intervals-for push ;

4
basis/compiler/cfg/linear-scan/assignment/assignment-tests.factor
View File

@ -53,7 +53,7 @@ IN: compiler.cfg.linear-scan.assignment.tests
{ V{ T{ ##spill { src RAX } { rep int-rep } } } } [
[
1234 int-regs <live-interval>
1234 <live-interval>
RAX >>reg int-rep >>spill-rep
insert-spill
] V{ } make
@ -85,7 +85,7 @@ IN: compiler.cfg.linear-scan.assignment.tests
] unit-test
{ 3 } [
{ 50 90 95 120 } [ 25 int-regs <live-interval> 2array ] map >min-heap
{ 50 90 95 120 } [ 25 <live-interval> 2array ] map >min-heap
pending-interval-heap set 90 expire-old-intervals
pending-interval-heap get heap-size
] unit-test

55
basis/compiler/cfg/linear-scan/linear-scan-tests.factor
View File

@ -73,7 +73,6 @@ H{
{
T{ live-interval-state
{ vreg 1 }
{ reg-class float-regs }
{ start 0 }
{ end 2 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } } }
@ -83,7 +82,6 @@ H{
}
T{ live-interval-state
{ vreg 1 }
{ reg-class float-regs }
{ start 5 }
{ end 5 }
{ uses V{ T{ vreg-use f 5 f float-rep } } }
@ -94,7 +92,6 @@ H{
} [
T{ live-interval-state
{ vreg 1 }
{ reg-class float-regs }
{ start 0 }
{ end 5 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
@ -107,7 +104,6 @@ H{
f
T{ live-interval-state
{ vreg 2 }
{ reg-class float-regs }
{ start 1 }
{ end 5 }
{ uses V{ T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
@ -118,7 +114,6 @@ H{
} [
T{ live-interval-state
{ vreg 2 }
{ reg-class float-regs }
{ start 0 }
{ end 5 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
@ -130,7 +125,6 @@ H{
{
T{ live-interval-state
{ vreg 3 }
{ reg-class float-regs }
{ start 0 }
{ end 2 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } } }
@ -142,7 +136,6 @@ H{
} [
T{ live-interval-state
{ vreg 3 }
{ reg-class float-regs }
{ start 0 }
{ end 5 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
@ -154,7 +147,6 @@ H{
{
T{ live-interval-state
{ vreg 4 }
{ reg-class float-regs }
{ start 0 }
{ end 1 }
{ uses V{ T{ vreg-use f 0 float-rep f } } }
@ -164,7 +156,6 @@ H{
}
T{ live-interval-state
{ vreg 4 }
{ reg-class float-regs }
{ start 20 }
{ end 30 }
{ uses V{ T{ vreg-use f 20 f float-rep } T{ vreg-use f 30 f float-rep } } }
@ -175,7 +166,6 @@ H{
} [
T{ live-interval-state
{ vreg 4 }
{ reg-class float-regs }
{ start 0 }
{ end 30 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 20 f float-rep } T{ vreg-use f 30 f float-rep } } }
@ -188,7 +178,6 @@ H{
{
T{ live-interval-state
{ vreg 5 }
{ reg-class float-regs }
{ start 0 }
{ end 1 }
{ uses V{ T{ vreg-use f 0 float-rep f } } }
@ -198,7 +187,6 @@ H{
}
T{ live-interval-state
{ vreg 5 }
{ reg-class float-regs }
{ start 20 }
{ end 30 }
{ uses V{ T{ vreg-use f 20 float-rep f } T{ vreg-use f 30 f float-rep } } }
@ -207,7 +195,6 @@ H{
} [
T{ live-interval-state
{ vreg 5 }
{ reg-class float-regs }
{ start 0 }
{ end 30 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 20 float-rep f } T{ vreg-use f 30 f float-rep } } }
@ -220,7 +207,6 @@ H{
{
T{ live-interval-state
{ vreg 6 }
{ reg-class float-regs }
{ start 0 }
{ end 11 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 10 double-rep float-rep } } }
@ -230,7 +216,6 @@ H{
}
T{ live-interval-state
{ vreg 6 }
{ reg-class float-regs }
{ start 20 }
{ end 20 }
{ uses V{ T{ vreg-use f 20 f double-rep } } }
@ -241,7 +226,6 @@ H{
} [
T{ live-interval-state
{ vreg 6 }
{ reg-class float-regs }
{ start 0 }
{ end 20 }
{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 10 double-rep float-rep } T{ vreg-use f 20 f double-rep } } }
@ -258,7 +242,6 @@ H{
{ end 8 }
{ ranges V{ T{ live-range f 8 8 } } }
{ uses V{ T{ vreg-use f 8 int-rep } } }
{ reg-class int-regs }
}
} [
T{ live-interval-state
@ -267,7 +250,6 @@ H{
{ end 8 }
{ ranges V{ T{ live-range f 4 8 } } }
{ uses V{ T{ vreg-use f 8 int-rep } } }
{ reg-class int-regs }
} 4 split-for-spill
clean-up-split
] unit-test
@ -280,7 +262,6 @@ H{
{ end 3 }
{ ranges V{ T{ live-range f 0 3 } } }
{ uses V{ T{ vreg-use f 0 f int-rep } T{ vreg-use f 2 f int-rep } } }
{ reg-class int-regs }
{ spill-to T{ spill-slot f 32 } }
{ spill-rep int-rep }
}
@ -290,7 +271,6 @@ H{
{ end 16 }
{ ranges V{ T{ live-range f 14 16 } } }
{ uses V{ T{ vreg-use f 14 f int-rep } } }
{ reg-class int-regs }
{ reload-from T{ spill-slot f 32 } }
{ reload-rep int-rep }
}
@ -300,8 +280,12 @@ H{
{ start 0 }
{ end 16 }
{ ranges V{ T{ live-range f 0 4 } T{ live-range f 6 10 } T{ live-range f 12 16 } } }
{ uses V{ T{ vreg-use f 0 f int-rep } T{ vreg-use f 2 f int-rep } T{ vreg-use f 14 f int-rep } } }
{ reg-class int-regs }
{ uses
V{
T{ vreg-use f 0 f int-rep }
T{ vreg-use f 2 f int-rep }
T{ vreg-use f 14 f int-rep } }
}
} 8 split-for-spill
clean-up-split
] unit-test
@ -323,7 +307,6 @@ H{
V{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ reg 1 }
{ start 1 }
{ end 15 }
@ -331,7 +314,6 @@ H{
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ reg 2 }
{ start 3 }
{ end 8 }
@ -339,7 +321,6 @@ H{
}
T{ live-interval-state
{ vreg 3 }
{ reg-class int-regs }
{ reg 3 }
{ start 3 }
{ end 10 }
@ -351,7 +332,6 @@ H{
H{ } inactive-intervals set
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 5 }
{ end 5 }
{ uses V{ T{ vreg-use f 5 int-rep f } } }
@ -370,7 +350,6 @@ H{
V{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ reg 1 }
{ start 1 }
{ end 15 }
@ -378,7 +357,6 @@ H{
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ reg 2 }
{ start 3 }
{ end 8 }
@ -390,7 +368,6 @@ H{
H{ } inactive-intervals set
T{ live-interval-state
{ vreg 3 }
{ reg-class int-regs }
{ start 5 }
{ end 5 }
{ uses V{ T{ vreg-use f 5 int-rep f } } }
@ -404,7 +381,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 100 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
@ -419,7 +395,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 10 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } } }
@ -427,7 +402,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 11 }
{ end 20 }
{ uses V{ T{ vreg-use f 11 int-rep f } T{ vreg-use f 20 f int-rep } } }
@ -442,7 +416,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 100 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
@ -450,7 +423,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 30 }
{ end 60 }
{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 60 f int-rep } } }
@ -465,7 +437,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 100 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
@ -473,7 +444,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 30 }
{ end 200 }
{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 200 f int-rep } } }
@ -488,7 +458,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 100 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
@ -496,7 +465,6 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 30 }
{ end 100 }
{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 100 f int-rep } } }
@ -520,7 +488,6 @@ H{
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 20 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } T{ vreg-use f 20 f int-rep } } }
@ -528,7 +495,6 @@ H{
}
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 0 }
{ end 20 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } T{ vreg-use f 20 f int-rep } } }
@ -536,7 +502,6 @@ H{
}
T{ live-interval-state
{ vreg 3 }
{ reg-class int-regs }
{ start 4 }
{ end 8 }
{ uses V{ T{ vreg-use f 6 int-rep f } } }
@ -544,7 +509,6 @@ H{
}
T{ live-interval-state
{ vreg 4 }
{ reg-class int-regs }
{ start 4 }
{ end 8 }
{ uses V{ T{ vreg-use f 8 int-rep f } } }
@ -554,7 +518,6 @@ H{
! This guy will invoke the 'spill partially available' code path
T{ live-interval-state
{ vreg 5 }
{ reg-class int-regs }
{ start 4 }
{ end 8 }
{ uses V{ T{ vreg-use f 8 int-rep f } } }
@ -571,7 +534,6 @@ H{
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 10 }
{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 6 f int-rep } T{ vreg-use f 10 f int-rep } } }
@ -581,7 +543,6 @@ H{
! This guy will invoke the 'spill new' code path
T{ live-interval-state
{ vreg 5 }
{ reg-class int-regs }
{ start 2 }
{ end 8 }
{ uses V{ T{ vreg-use f 8 int-rep f } } }
@ -607,7 +568,6 @@ H{
{
T{ live-interval-state
{ vreg 1 }
{ reg-class int-regs }
{ start 0 }
{ end 20 }
{ reg 0 }
@ -617,7 +577,6 @@ H{
T{ live-interval-state
{ vreg 2 }
{ reg-class int-regs }
{ start 4 }
{ end 40 }
{ reg 0 }
@ -632,7 +591,6 @@ H{
{
T{ live-interval-state
{ vreg 3 }
{ reg-class int-regs }
{ start 0 }
{ end 40 }
{ reg 1 }
@ -645,7 +603,6 @@ H{
T{ live-interval-state
{ vreg 4 }
{ reg-class int-regs }
{ start 8 }
{ end 10 }
{ ranges V{ T{ live-range f 8 10 } } }

5
basis/compiler/cfg/linear-scan/live-intervals/live-intervals-docs.factor
View File

@ -6,7 +6,6 @@ IN: compiler.cfg.linear-scan.live-intervals
HELP: <live-interval>
{ $values
{ "vreg" "virtual register" }
{ "reg-class" "register class" }
{ "live-interval" live-interval-state }
}
{ $description "Creates a new live interval for a virtual register. Initially the range is empty." } ;
@ -78,6 +77,10 @@ HELP: live-interval-state
HELP: live-intervals
{ $var-description "Mapping from vreg to " { $link live-interval-state } "." } ;
HELP: record-temp
{ $values { "vreg" number } { "n" number } }
{ $description "Assigns the interval [n,n] to vreg:s live interval." } ;
HELP: sync-point
{ $class-description "A location where all registers have to be spilled. For example when garbage collection is run or an alien ffi call is invoked. Figuring out where in the " { $link cfg } " the sync points are is done in the " { $link compute-live-intervals } " step. The tuple has the following slots:"
{ $table

7
basis/compiler/cfg/linear-scan/live-intervals/live-intervals-tests.factor
View File

@ -7,7 +7,7 @@ fry kernel namespaces sequences tools.test ;
IN: compiler.cfg.linear-scan.live-intervals.tests
: <live-interval-for-ranges> ( ranges -- live-interval )
10 int-rep <live-interval> [ '[ first2 _ ranges>> add-range ] each ] keep
10 <live-interval> [ '[ first2 _ ranges>> add-range ] each ] keep
dup compute-start/end ;
! cfg>sync-points
@ -42,7 +42,6 @@ IN: compiler.cfg.linear-scan.live-intervals.tests
{ vreg 8 }
{ ranges V{ T{ live-range { from -10 } { to 23 } } } }
{ uses V{ } }
{ reg-class int-regs }
}
}
{
@ -51,7 +50,6 @@ IN: compiler.cfg.linear-scan.live-intervals.tests
{ vreg 9 }
{ ranges V{ T{ live-range { from -10 } { to 23 } } } }
{ uses V{ } }
{ reg-class int-regs }
}
}
{
@ -60,7 +58,6 @@ IN: compiler.cfg.linear-scan.live-intervals.tests
{ vreg 4 }
{ ranges V{ T{ live-range { from -10 } { to 23 } } } }
{ uses V{ } }
{ reg-class int-regs }
}
}
}
@ -81,14 +78,12 @@ IN: compiler.cfg.linear-scan.live-intervals.tests
} [
T{ live-interval-state
{ start 0 }
{ reg-class int-regs }
{ end 10 }
{ uses { 0 10 } }
{ ranges V{ T{ live-range f 0 10 } } }
}
T{ live-interval-state
{ start 5 }
{ reg-class int-regs }
{ end 10 }
{ uses { 5 10 } }
{ ranges V{ T{ live-range f 5 10 } } }

12
basis/compiler/cfg/linear-scan/live-intervals/live-intervals.factor
View File

@ -15,8 +15,7 @@ TUPLE: vreg-use n def-rep use-rep spill-slot? ;
TUPLE: live-interval-state
vreg
reg spill-to spill-rep reload-from reload-rep
start end ranges uses
reg-class ;
start end ranges uses ;
: first-use ( live-interval -- use ) uses>> first ; inline
@ -43,11 +42,10 @@ TUPLE: live-interval-state
insn# live-interval (find-use)
dup [ dup n>> insn# = [ drop f ] unless ] when ;
: <live-interval> ( vreg reg-class -- live-interval )
: <live-interval> ( vreg -- live-interval )
\ live-interval-state new
V{ } clone >>uses
V{ } clone >>ranges
swap >>reg-class
swap >>vreg ;
: block-from ( bb -- n ) instructions>> first insn#>> 1 - ;
@ -59,8 +57,10 @@ SYMBOLS: from to ;
SYMBOL: live-intervals
: live-interval ( vreg -- live-interval )
leader live-intervals get
[ dup rep-of reg-class-of <live-interval> ] cache ;
leader live-intervals get [ <live-interval> ] cache ;
: interval-reg-class ( live-interval -- reg-class )
vreg>> rep-of reg-class-of ;
GENERIC: compute-live-intervals* ( insn -- )