Dead code elimination eliminates some dead allocations

basis/compiler/cfg/dce/authors.txt

@@ -1 +1,2 @@
-Slava Pestov
+Slava Pestov
+Daniel Ehrenberg

basis/compiler/cfg/dce/dce-tests.factor

@@ -0,0 +1,60 @@
+! Copyright (C) 2009 Daniel Ehrenberg.
+! See http://factorcode.org/license.txt for BSD license.
+USING: tools.test compiler.cfg kernel accessors compiler.cfg.dce
+compiler.cfg.instructions compiler.cfg.registers cpu.architecture ;
+IN: compiler.cfg.dce.tests
+
+: test-dce ( insns -- insns' )
+    <basic-block> swap >>instructions
+    cfg new swap >>entry
+    eliminate-dead-code
+    entry>> instructions>> ; 
+
+[ V{
+    T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
+    T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
+    T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
+    T{ ##replace { src V int-regs 3 } { loc D 0 } }
+} ] [ V{
+    T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
+    T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
+    T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
+    T{ ##replace { src V int-regs 3 } { loc D 0 } }
+} test-dce ] unit-test
+
+[ V{ } ] [ V{
+    T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
+    T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
+    T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
+} test-dce ] unit-test
+
+[ V{ } ] [ V{
+    T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+} test-dce ] unit-test
+
+[ V{ } ] [ V{
+    T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+    T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+} test-dce ] unit-test
+
+[ V{
+    T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+    T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+    T{ ##replace { src V int-regs 1 } { loc D 0 } }
+} ] [ V{
+    T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+    T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+    T{ ##replace { src V int-regs 1 } { loc D 0 } }
+} test-dce ] unit-test
+
+[ V{
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+    T{ ##replace { src V int-regs 1 } { loc D 0 } }
+} ] [ V{
+    T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+    T{ ##replace { src V int-regs 1 } { loc D 0 } }
+} test-dce ] unit-test

basis/compiler/cfg/dce/dce.factor

@@ -1,4 +1,4 @@
-! Copyright (C) 2008, 2009 Slava Pestov.
+! Copyright (C) 2008, 2009 Slava Pestov, Daniel Ehrenberg.
 ! See http://factorcode.org/license.txt for BSD license.
 USING: accessors assocs sets kernel namespaces sequences
 compiler.cfg.instructions compiler.cfg.def-use
@@ -11,29 +11,64 @@ SYMBOL: liveness-graph
 ! vregs which participate in side effects and thus are always live
 SYMBOL: live-vregs
 
+! vregs which are the result of an allocation
+SYMBOL: allocate
+
 : init-dead-code ( -- )
     H{ } clone liveness-graph set
-    H{ } clone live-vregs set ;
+    H{ } clone live-vregs set
+    H{ } clone allocate set ;
 
 GENERIC: update-liveness-graph ( insn -- )
 
-M: ##flushable update-liveness-graph
+: add-edges ( insn register -- )
-    [ uses-vregs ] [ dst>> ] bi liveness-graph get set-at ;
+    [ uses-vregs ] dip liveness-graph get [ union ] change-at ;
 
-: record-live ( vregs -- )
+M: ##flushable update-liveness-graph
+    dup dst>> add-edges ;
+
+: (record-live) ( vregs -- )
     [
         dup live-vregs get key? [ drop ] [
             [ live-vregs get conjoin ]
-            [ liveness-graph get at record-live ]
+            [ liveness-graph get at (record-live) ]
             bi
         ] if
     ] each ;
 
-M: insn update-liveness-graph uses-vregs record-live ;
+: record-live ( insn -- )
+    uses-vregs (record-live) ;
+
+M: insn update-liveness-graph record-live ;
+
+: update-allocator-liveness ( insn vreg -- )
+    dup allocate get key? [ add-edges ] [ drop record-live ] if ;
+
+M: ##set-slot update-liveness-graph
+    dup obj>> update-allocator-liveness ;
+
+M: ##set-slot-imm update-liveness-graph
+    dup obj>> update-allocator-liveness ;
+
+M: ##write-barrier update-liveness-graph
+    dup src>> update-allocator-liveness ;
+
+M: ##allot update-liveness-graph
+    [ dst>> allocate get conjoin ]
+    [ call-next-method ] bi ;
 
 GENERIC: live-insn? ( insn -- ? )
 
-M: ##flushable live-insn? dst>> live-vregs get key? ;
+: live-vreg? ( vreg -- ? )
+    live-vregs get key? ;
+
+M: ##flushable live-insn? dst>> live-vreg? ;
+
+M: ##set-slot live-insn? obj>> live-vreg? ;
+
+M: ##set-slot-imm live-insn? obj>> live-vreg? ;
+
+M: ##write-barrier live-insn? src>> live-vreg? ;
 
 M: insn live-insn? drop t ;
 
@@ -42,4 +77,4 @@ M: insn live-insn? drop t ;
     [ [ instructions>> [ update-liveness-graph ] each ] each-basic-block ]
     [ [ [ [ live-insn? ] filter ] change-instructions drop ] each-basic-block ]
     [ ]
-    tri ;
+    tri ;

basis/compiler/cfg/dce/summary.txt

@@ -0,0 +1 @@
+Dead code elimination