2577ab83a6
only emit ##alien-vector/##set-alien-vector insns if the rep is available
2009-10-10 12:53:10 -05:00
5158a12d32
rename ##shuffle-vector to ##shuffle-vector-imm, and add a new ##shuffle-vector for dynamic shuffles. have vshuffle use ##shuffle-vector to do word and byte shuffles on x86
2009-10-09 21:26:27 -05:00
5f0d4abb4a
cpu.architecture: move dummy -reps words here, from cpu.ppc
2009-10-08 03:48:03 -05:00
98836a9e2e
break vector compare intrinsics into %compare, %or, and %not instructions that map directly to cpu instructions
2009-10-07 15:27:03 -05:00
43b51ef2eb
decompose %unpack-vector-head/tail into %compare-vector/%merge-vector-head/tail or %tail>head-vector/%unpack-vector-head insns when there isn't an actual unpack insn; get rid of fake x86 implementations
2009-10-07 14:09:46 -05:00
444624e79f
fix x86 %unpack-vector insns
2009-10-06 20:38:51 -05:00
84ecb1266d
add insns for vector pack, unpack, integer>float, and float>integer
2009-10-05 22:34:14 -05:00
931107397c
compiler.cfg: remove _gc instruction, it doesn't need to exist, and change GC checks to ensure that the right amount of space is available instead of blindly checking for 1Kb
2009-10-05 05:27:49 -05:00
dca9d3e535
add %merge-vector-head and %merge-vector-tail instructions to back vmerge
2009-10-03 21:48:53 -05:00
335df20713
add intrinsics for v<=, v<, v=, v>, v>=, vunordered?
2009-10-03 11:29:34 -05:00
b1ec36a324
extend x86 %compare-vector to cover all comparison codes, sometimes stupidly for now
2009-10-02 23:19:56 -05:00
e2e75c6b3a
add intrinsic for vnot/vbitnot
2009-10-02 20:04:28 -05:00
9d424a1092
Merge branch 'master' of git://factorcode.org/git/factor
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Conflicts:
basis/compiler/codegen/codegen.factor
2009-10-01 23:14:16 -05:00
7b13fa4283
fold test-vector/branch sequences into a test-vector-branch instruction
2009-10-01 19:53:30 -05:00
228ad950bb
%test-vector instruction for vany?, vall?, vnone?
2009-10-01 15:35:38 -05:00
94070c11aa
%compare-vector instruction (only does v= for now)
2009-10-01 14:31:37 -05:00
3ba79be651
Revert "add a %blend-vector intrinsic for v?"
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This reverts commit 21e4b28b67
2009-09-30 23:40:37 -05:00
21e4b28b67
add a %blend-vector intrinsic for v?
2009-09-30 23:03:59 -05:00
8e201ca4b7
Various minor compiler tweaks: Combine address calculation with dereferencing in alien accessors; convert SIMD XOR of a vector with itself into an XOR of the destination with itself; convert SIMD unbox of zero vector into XOR of the destination with itself; fix SIMD indexing on x86-64
2009-09-30 05:00:36 -05:00
2b13245704
math.vectors.simd: add fast intrinsic for 'nth', replace broadcast primitive with shuffles
2009-09-29 04:48:11 -05:00
db217295b0
Work in progress
2009-09-28 17:31:34 -05:00
10c5fe5933
math.vectors.simd: add hlshift, hrshift (128-bit shift), vbitandn intrinsics
2009-09-28 02:17:46 -05:00
e8cfaccef0
compiler.cfg: nuke ##bignum>integer and ##integer>bignum since they were unused
2009-09-27 20:36:05 -05:00
6dd8e4657e
Merge branch 'master' into more_aggressive_coalescing
2009-09-27 19:29:50 -05:00
6f2a4eba51
compiler.cfg.linear-scan: fix partial sync point logic in case where dst == src, and clean up spilling code
2009-09-27 19:28:20 -05:00
a267100781
compiler.cfg.ssa.destruction: more aggressive coalescing work in progress
2009-09-27 17:17:26 -05:00
2b35f52ed2
Merge branch 'slots' of git://factorcode.org/git/factor into slots
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Conflicts:
basis/cpu/x86/x86.factor
2009-09-26 03:12:42 -05:00
364332bd70
Completing slot and set-slot changes on x86
2009-09-26 01:39:48 -05:00
5b404aae7e
moved %(un)nest-stacks out to cpu specific files to eliminate %vm-invoke from compiler.codegen
2009-09-25 19:32:08 +01:00
f9e736c1f0
isolated %vm-invoke-blah-arg crap to 64.factor
2009-09-25 19:02:41 +01:00
c0957ed908
compiler.codegen passes temp reg to %call-gc
2009-09-25 18:48:13 +01:00
24039cb56a
math.vectors.simd: add v<< and v>> intrinsics for bitwise shifts on elements
2009-09-24 03:32:39 -05:00
165496d2f2
Add longlong-2, ulonglong-2, longlong-4, ulonglong-4 SIMD types, fix int-4 multiplication on SSE2
2009-09-23 20:23:25 -05:00
abac963882
math.vectors.simd: new operations: vabs vsqrt vbitand vbitor vbitxor
2009-09-23 02:47:14 -05:00
e04fba6bc7
Fix conflict
2009-09-20 23:18:07 -05:00
66871995c9
math.vectors.simd: add saturated arithmetic operations
2009-09-20 23:16:02 -05:00
78c949b9b7
math.vectors: add v+- word which is accelerated by SSE3
2009-09-20 17:43:16 -05:00
ea2bcd69c7
math.vectors.simd: redesign to be more flexible, integer SIMD work in progress
2009-09-20 02:08:32 -05:00
f5e6d43e1e
separated vm-1st-arg and vm-3rd-arg asm invoke words (needed for ppc & x86.64)
2009-09-16 08:20:09 +01:00
780415b159
added code to pass vm ptr to some unboxers
2009-09-16 08:16:32 +01:00
2a1a4ccf27
fixed up getenv compiler intrinsic to use vm struct userenv
2009-09-16 08:16:32 +01:00
1fda8af73b
Added %vm-invoke to pass vm ptr to vm functions (x86.32 only, otherwise uses singleton vm)
2009-09-16 08:16:30 +01:00
092b31910d
compiler: separate ##save-context instruction from ##alien-invoke, generate a ##save-context for libm calls, and add a pass to combine multiple context saves within a basic block. Fixes crashes with FP traps thrown by libm functions on x86-32
2009-09-08 21:50:55 -05:00
025a5b7b15
split unordered and ordered float comparison intrinsics in compiler; generate only unordered comparisons for now
2009-09-08 17:04:26 -05:00
8eeeeb5c5b
inline alien-vector and set-alien-vector if SIMD is not available for a small speedup
2009-09-08 13:56:17 -05:00
1f5193198b
compiler: clean up code generation for alien boxing/unboxing a bit
2009-09-03 21:22:43 -05:00
20dfbf7ac8
More SIMD work
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- Rename SIMD types and register representations: <type>-<count> rather than <count><type>-array
- Make a functor to define 256-bit vector types, use it to define float-8 type
- Make SIMD instructions pure-insns so that they participate in value numbering
2009-09-03 20:58:56 -05:00
52b99c050e
Initial implementation of SSE vector intrinsics:
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- cpu.architecture: add SSE vector representations
- compiler.cfg.intrinsics.alien: remove an attempt at optimization that value numbering handles now
- compiler.cfg.representations: support instructions where the representation is set in the 'rep' slot, and support conversions between single and double floats
- alien-float, set-alien-float now use the single float representation, and the conversion is implicit; this fixes a long-standing bug where a register could get clobbered because of how %set-alien-float was defined on x86
- math.vectors.specialization: add support for SIMD specialization (where the vector word's body is replaced by another quotation), also specialize the 'sum' word
- math.vectors.simd: 4float-array, 2double-array, 4double-array types, and specializers for the math.vectors words
2009-09-03 02:33:07 -05:00
775b9af2f7
compiler: eliminate boilerplate by centralizing info in declarative INSN: syntax
2009-09-02 06:22:37 -05:00
b35a01879e
%box-displaced-alien: fix clobberage found by Doug
2009-08-30 05:11:08 -05:00
Joe Groff
Slava Pestov
Slava Pestov
sheeple
Daniel Ehrenberg
Phil Dawes