Commit Graph

16 Commits (a5e4eb1948f0087bab9279c29e61913223566227)

Author SHA1 Message Date
Slava Pestov a5e4eb1948 cpu.x86.assembler: support all addressing modes 2010-05-03 17:34:06 -04:00
Slava Pestov 639a1f7043 cpu.x86.assembler: add support for absolute addressing on x86-64; [RIP+] now behaves like [] did, and [] now does absolute addressing just like in 32-bit mode 2010-04-04 19:42:57 -04:00
Slava Pestov a8eeff7c48 cpu.x86.assembler: add segment override prefixes 2010-03-31 20:47:13 -04:00
Joe Groff 467c389948 cpu.x86.assembler: make SSE shuffle instructions accept an array of indexes so they're easier to use 2009-09-28 11:45:45 -05:00
Joe Groff b49fb43b60 Merge branch 'master' of git://factorcode.org/git/factor 2009-07-30 11:05:36 -05:00
Joe Groff c59c619364 add additional SSE2 packed integer operations 2009-07-30 11:05:12 -05:00
Slava Pestov 226908d2d2 cpu.x86.assembler: fix extended 8-bit registers (DIL, SIL, SPL, BPL) 2009-07-29 22:32:22 -05:00
Slava Pestov 7831293fda cpu.x86.assembler: move operands to operands sub-vocabulary, clean up small-reg-* code in compiler backend 2009-07-29 21:44:08 -05:00
Joe Groff 4c664a469a SSE4 opcodes for x86 assembler 2009-07-28 12:19:37 -05:00
Joe Groff 1fe11f7c87 SSE1–SSSE3 opcodes + branch hints for x86 assembler 2009-07-28 00:22:27 -05:00
Slava Pestov a61a992bfd cpu.x86.assembler: IMUL2 instruction was busted for immediate operands
When given a register and an immediate, it would generate imul imm,dst,dst however the 64-bit prefix was generated wrong and if dst was an extended register only the first operand would be an extended register. To fix this, change IMUL2 to not work on immediates anymore, and added a new IMUL3 that takes a destination register, source register, and immediate. Also, change compiler.cfg.two-operand to not two-operandize %mul-imm, since this isn't needed anymore.
This fixes the sporadic benchmark.tuple-arrays crash on 64-bit machines.
2009-06-08 21:15:52 -05:00
Slava Pestov 5188f4e1f0 Fix TEST opcode in cpu.x86.assembler 2009-04-29 22:23:42 -05:00
Slava Pestov abb02f1784 Flesh out shift instructions 2008-11-03 00:03:00 -06:00
Slava Pestov 52020c2fe3 Fixing x86 instruction encoding for addressing with base = ESP or R12 2008-10-21 23:18:27 -05:00
Slava Pestov 0c8e2584b4 Fixing unit tests for make, fry changes 2008-09-11 00:20:06 -05:00
Slava Pestov d66f887736 Create basis vocab root 2008-07-28 22:03:13 -05:00