e04df76f60
Various codegen improvements:
...
- new-insn word to construct instructions
- cache RPO in the CFG
- re-organize low-level optimizer so that MR is built after register allocation
- register allocation now stores instruction numbers in the instructions themselves
- split defs-vregs into defs-vregs and temp-vregs
2009-05-29 13:11:34 -05:00
ca2f01e0d0
Updating non-core libraries for monotonic? change
2009-01-16 17:02:54 -06:00
34792a9f23
Remove >r/r>
2008-12-17 19:17:37 -06:00
1af3b8ed65
If a register is spilled and the reload location is also a copy, we chicken out and don't coalesce. This is suboptimal but it's not clear to me how to implement it cleanly, and SSA graph coloring will solve this problem eventually anyway
2008-11-04 00:32:56 -06:00
0250d7c1d2
Forgot a drop in unit test
2008-11-03 01:53:27 -06:00
8df1aba71d
Coalescing
2008-11-02 01:49:57 -06:00
e92f795a76
More work on intrinsics; memory allocation and slot access now expands correctly
2008-10-20 20:40:15 -05:00
c0d89b061e
Fixing register allocator prspilling
2008-10-19 01:10:21 -05:00
749c77d6b1
Fix linear scan test
2008-10-12 18:40:10 -05:00
cf46a832e7
Debugging register allocator and inline allocation
2008-10-08 23:42:53 -05:00
f436fd0c0f
Merging in new codegen
2008-10-07 16:16:50 -05:00
Slava Pestov