factor

Author	SHA1	Message	Date
Slava Pestov	e04df76f60	Various codegen improvements: - new-insn word to construct instructions - cache RPO in the CFG - re-organize low-level optimizer so that MR is built after register allocation - register allocation now stores instruction numbers in the instructions themselves - split defs-vregs into defs-vregs and temp-vregs	2009-05-29 13:11:34 -05:00
Slava Pestov	ab689c098b	Clean up direct literal code and make a first attempt at PowerPC support	2008-11-24 08:16:14 -06:00
Slava Pestov	eb05dd3a12	Optimize a ##dispatch that is applied to the result of a ##sub-imm or ##add-imm; this eliminates an instruction from the common 1 fixnum-fast { ... } dispatch and 8 fixnum-fast { ... } dispatch code sequences appearing in generic word expansions	2008-11-13 04:16:08 -06:00
Slava Pestov	64cbf619a9	Add more algebraic simplifications: comparison of a comparison, comparison where first is immediate	2008-11-06 09:27:52 -06:00
Slava Pestov	492a15e345	Move insn class to compiler.cfg.instructions	2008-10-24 09:17:06 -05:00
Slava Pestov	885adc8dc9	Various improvements	2008-10-23 05:27:54 -05:00
Slava Pestov	52967c5bf1	Improved value numbering	2008-10-23 02:49:26 -05:00