143 lines
3.9 KiB
C++
143 lines
3.9 KiB
C++
namespace factor {
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enum relocation_type {
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// arg is a literal table index, holding a pair (symbol/dll)
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RT_DLSYM,
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// a word or quotation's general entry point
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RT_ENTRY_POINT,
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// a word's PIC entry point
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RT_ENTRY_POINT_PIC,
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// a word's tail-call PIC entry point
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RT_ENTRY_POINT_PIC_TAIL,
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// current offset
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RT_HERE,
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// current code block
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RT_THIS,
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// data heap literal
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RT_LITERAL,
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// untagged fixnum literal
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RT_UNTAGGED,
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// address of megamorphic_cache_hits var
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RT_MEGAMORPHIC_CACHE_HITS,
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// address of vm object
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RT_VM,
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// value of vm->cards_offset
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RT_CARDS_OFFSET,
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// value of vm->decks_offset
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RT_DECKS_OFFSET,
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RT_UNUSED,
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// arg is a literal table index, holding a pair (symbol/dll)
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RT_DLSYM_TOC,
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// address of inline_cache_miss function. This is a separate
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// relocation to reduce compile time and size for PICs.
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RT_INLINE_CACHE_MISS,
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// address of safepoint page in code heap
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RT_SAFEPOINT
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};
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enum relocation_class {
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// absolute address in a pointer-width location
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RC_ABSOLUTE_CELL,
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// absolute address in a 4 byte location
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RC_ABSOLUTE,
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// relative address in a 4 byte location
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RC_RELATIVE,
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// absolute address in a PowerPC LIS/ORI sequence
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RC_ABSOLUTE_PPC_2_2,
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// absolute address in a PowerPC LWZ instruction
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RC_ABSOLUTE_PPC_2,
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// relative address in a PowerPC LWZ/STW/BC instruction
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RC_RELATIVE_PPC_2_PC,
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// relative address in a PowerPC B/BL instruction
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RC_RELATIVE_PPC_3_PC,
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// relative address in an ARM B/BL instruction
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RC_RELATIVE_ARM_3,
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// pointer to address in an ARM LDR/STR instruction
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RC_INDIRECT_ARM,
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// pointer to address in an ARM LDR/STR instruction offset by 8 bytes
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RC_INDIRECT_ARM_PC,
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// absolute address in a 2 byte location
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RC_ABSOLUTE_2,
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// absolute address in a 1 byte location
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RC_ABSOLUTE_1,
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// absolute address in a PowerPC LIS/ORI/SLDI/ORIS/ORI sequence
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RC_ABSOLUTE_PPC_2_2_2_2,
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};
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static const cell rel_absolute_ppc_2_mask = 0x0000ffff;
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static const cell rel_relative_ppc_2_mask = 0x0000fffc;
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static const cell rel_relative_ppc_3_mask = 0x03fffffc;
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static const cell rel_indirect_arm_mask = 0x00000fff;
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static const cell rel_relative_arm_3_mask = 0x00ffffff;
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// code relocation table consists of a table of entries for each fixup
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struct relocation_entry {
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uint32_t value;
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explicit relocation_entry(uint32_t value) : value(value) {}
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relocation_entry(relocation_type rel_type, relocation_class rel_class,
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cell offset) {
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value = (uint32_t)((rel_type << 28) | (rel_class << 24) | offset);
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}
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relocation_type type() {
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return (relocation_type)((value & 0xf0000000) >> 28);
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}
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relocation_class klass() {
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return (relocation_class)((value & 0x0f000000) >> 24);
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}
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cell offset() { return (value & 0x00ffffff); }
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int number_of_parameters() {
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switch (type()) {
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case RT_VM:
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return 1;
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case RT_DLSYM:
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case RT_DLSYM_TOC:
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return 2;
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case RT_ENTRY_POINT:
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case RT_ENTRY_POINT_PIC:
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case RT_ENTRY_POINT_PIC_TAIL:
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case RT_LITERAL:
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case RT_HERE:
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case RT_UNTAGGED:
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case RT_THIS:
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case RT_MEGAMORPHIC_CACHE_HITS:
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case RT_CARDS_OFFSET:
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case RT_DECKS_OFFSET:
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case RT_INLINE_CACHE_MISS:
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case RT_SAFEPOINT:
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return 0;
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default:
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critical_error("Bad rel type in number_of_parameters()", type());
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return -1; // Can't happen
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}
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}
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};
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struct instruction_operand {
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relocation_entry rel;
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code_block* compiled;
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cell index;
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cell pointer;
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instruction_operand(relocation_entry rel, code_block* compiled,
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cell index);
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fixnum load_value_2_2();
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fixnum load_value_2_2_2_2();
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fixnum load_value_masked(cell mask, cell bits, cell shift);
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fixnum load_value(cell relative_to);
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code_block* load_code_block();
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void store_value_2_2(fixnum value);
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void store_value_2_2_2_2(fixnum value);
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void store_value_masked(fixnum value, cell mask, cell shift);
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void store_value(fixnum value);
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};
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}
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