421 lines
8.2 KiB
Factor
421 lines
8.2 KiB
Factor
! Copyright (C) 2005, 2009 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: kernel namespaces words math math.order locals
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cpu.ppc.assembler.backend ;
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IN: cpu.ppc.assembler
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! See the Motorola or IBM documentation for details. The opcode
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! names are standard, and the operand order is the same as in
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! the docs, except a few differences, namely, in IBM/Motorola
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! assembler syntax, loads and stores are written like:
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!
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! stw r14,10(r15)
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!
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! In Factor, we write:
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!
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! 14 15 10 STW
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! D-form
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D: ADDI 14
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D: ADDIC 12
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D: ADDIC. 13
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D: ADDIS 15
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D: CMPI 11
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D: CMPLI 10
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D: LBZ 34
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D: LBZU 35
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D: LFD 50
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D: LFDU 51
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D: LFS 48
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D: LFSU 49
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D: LHA 42
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D: LHAU 43
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D: LHZ 40
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D: LHZU 41
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D: LWZ 32
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D: LWZU 33
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D: MULI 7
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D: MULLI 7
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D: STB 38
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D: STBU 39
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D: STFD 54
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D: STFDU 55
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D: STFS 52
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D: STFSU 53
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D: STH 44
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D: STHU 45
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D: STW 36
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D: STWU 37
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! SD-form
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SD: ANDI 28
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SD: ANDIS 29
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SD: ORI 24
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SD: ORIS 25
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SD: XORI 26
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SD: XORIS 27
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! X-form
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X: AND 0 28 31
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X: AND. 1 28 31
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X: CMP 0 0 31
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X: CMPL 0 32 31
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X: EQV 0 284 31
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X: EQV. 1 284 31
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X: FCMPO 0 32 63
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X: FCMPU 0 0 63
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X: LBZUX 0 119 31
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X: LBZX 0 87 31
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X: LHAUX 0 375 31
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X: LHAX 0 343 31
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X: LHZUX 0 311 31
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X: LHZX 0 279 31
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X: LWZUX 0 55 31
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X: LWZX 0 23 31
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X: NAND 0 476 31
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X: NAND. 1 476 31
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X: NOR 0 124 31
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X: NOR. 1 124 31
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X: OR 0 444 31
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X: OR. 1 444 31
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X: ORC 0 412 31
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X: ORC. 1 412 31
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X: SLW 0 24 31
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X: SLW. 1 24 31
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X: SRAW 0 792 31
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X: SRAW. 1 792 31
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X: SRAWI 0 824 31
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X: SRW 0 536 31
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X: SRW. 1 536 31
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X: STBUX 0 247 31
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X: STBX 0 215 31
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X: STHUX 0 439 31
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X: STHX 0 407 31
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X: STWUX 0 183 31
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X: STWX 0 151 31
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X: XOR 0 316 31
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X: XOR. 1 316 31
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X1: EXTSB 0 954 31
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X1: EXTSB. 1 954 31
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: FRSP ( a s -- ) [ 0 ] 2dip 0 12 63 x-insn ;
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: FRSP. ( a s -- ) [ 0 ] 2dip 1 12 63 x-insn ;
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: FMR ( a s -- ) [ 0 ] 2dip 0 72 63 x-insn ;
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: FMR. ( a s -- ) [ 0 ] 2dip 1 72 63 x-insn ;
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: FCTIWZ ( a s -- ) [ 0 ] 2dip 0 15 63 x-insn ;
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: FCTIWZ. ( a s -- ) [ 0 ] 2dip 1 15 63 x-insn ;
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! XO-form
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XO: ADD 0 0 266 31
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XO: ADD. 0 1 266 31
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XO: ADDC 0 0 10 31
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XO: ADDC. 0 1 10 31
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XO: ADDCO 1 0 10 31
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XO: ADDCO. 1 1 10 31
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XO: ADDE 0 0 138 31
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XO: ADDE. 0 1 138 31
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XO: ADDEO 1 0 138 31
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XO: ADDEO. 1 1 138 31
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XO: ADDO 1 0 266 31
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XO: ADDO. 1 1 266 31
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XO: DIVW 0 0 491 31
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XO: DIVW. 0 1 491 31
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XO: DIVWO 1 0 491 31
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XO: DIVWO. 1 1 491 31
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XO: DIVWU 0 0 459 31
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XO: DIVWU. 0 1 459 31
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XO: DIVWUO 1 0 459 31
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XO: DIVWUO. 1 1 459 31
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XO: MULHW 0 0 75 31
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XO: MULHW. 0 1 75 31
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XO: MULHWU 0 0 11 31
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XO: MULHWU. 0 1 11 31
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XO: MULLW 0 0 235 31
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XO: MULLW. 0 1 235 31
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XO: MULLWO 1 0 235 31
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XO: MULLWO. 1 1 235 31
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XO: SUBF 0 0 40 31
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XO: SUBF. 0 1 40 31
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XO: SUBFC 0 0 8 31
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XO: SUBFC. 0 1 8 31
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XO: SUBFCO 1 0 8 31
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XO: SUBFCO. 1 1 8 31
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XO: SUBFE 0 0 136 31
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XO: SUBFE. 0 1 136 31
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XO: SUBFEO 1 0 136 31
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XO: SUBFEO. 1 1 136 31
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XO: SUBFO 1 0 40 31
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XO: SUBFO. 1 1 40 31
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XO1: NEG 0 0 104 31
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XO1: NEG. 0 1 104 31
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XO1: NEGO 1 0 104 31
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XO1: NEGO. 1 1 104 31
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! A-form
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: RLWINM ( d a b c xo -- ) 0 21 a-insn ;
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: RLWINM. ( d a b c xo -- ) 1 21 a-insn ;
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: FADD ( d a b -- ) 0 21 0 63 a-insn ;
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: FADD. ( d a b -- ) 0 21 1 63 a-insn ;
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: FSUB ( d a b -- ) 0 20 0 63 a-insn ;
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: FSUB. ( d a b -- ) 0 20 1 63 a-insn ;
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: FMUL ( d a c -- ) 0 swap 25 0 63 a-insn ;
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: FMUL. ( d a c -- ) 0 swap 25 1 63 a-insn ;
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: FDIV ( d a b -- ) 0 18 0 63 a-insn ;
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: FDIV. ( d a b -- ) 0 18 1 63 a-insn ;
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: FSQRT ( d b -- ) 0 swap 0 22 0 63 a-insn ;
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: FSQRT. ( d b -- ) 0 swap 0 22 1 63 a-insn ;
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! Branches
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: B ( dest -- ) 0 0 (B) ;
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: BL ( dest -- ) 0 1 (B) ;
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BC: LT 12 0
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BC: GE 4 0
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BC: GT 12 1
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BC: LE 4 1
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BC: EQ 12 2
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BC: NE 4 2
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BC: O 12 3
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BC: NO 4 3
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B: CLR 0 8 0 0 19
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B: CLRL 0 8 0 1 19
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B: CCTR 0 264 0 0 19
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: BLR ( -- ) 20 BCLR ;
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: BLRL ( -- ) 20 BCLRL ;
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: BCTR ( -- ) 20 BCCTR ;
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! Special registers
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MFSPR: XER 1
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MFSPR: LR 8
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MFSPR: CTR 9
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MTSPR: XER 1
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MTSPR: LR 8
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MTSPR: CTR 9
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! Pseudo-instructions
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: LI ( value dst -- ) swap [ 0 ] dip ADDI ; inline
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: SUBI ( dst src1 src2 -- ) neg ADDI ; inline
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: LIS ( value dst -- ) swap [ 0 ] dip ADDIS ; inline
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: SUBIC ( dst src1 src2 -- ) neg ADDIC ; inline
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: SUBIC. ( dst src1 src2 -- ) neg ADDIC. ; inline
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: NOT ( dst src -- ) dup NOR ; inline
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: NOT. ( dst src -- ) dup NOR. ; inline
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: MR ( dst src -- ) dup OR ; inline
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: MR. ( dst src -- ) dup OR. ; inline
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: (SLWI) ( d a b -- d a b x y ) 0 31 pick - ; inline
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: SLWI ( d a b -- ) (SLWI) RLWINM ;
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: SLWI. ( d a b -- ) (SLWI) RLWINM. ;
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: (SRWI) ( d a b -- d a b x y ) 32 over - swap 31 ; inline
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: SRWI ( d a b -- ) (SRWI) RLWINM ;
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: SRWI. ( d a b -- ) (SRWI) RLWINM. ;
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:: LOAD32 ( n r -- )
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n -16 shift HEX: ffff bitand r LIS
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r r n HEX: ffff bitand ORI ;
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: immediate? ( n -- ? ) HEX: -8000 HEX: 7fff between? ;
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: LOAD ( n r -- ) over immediate? [ LI ] [ LOAD32 ] if ;
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! Altivec/VMX instructions
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VA: VMHADDSHS 32 4
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VA: VMHRADDSHS 33 4
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VA: VMLADDUHM 34 4
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VA: VMSUMUBM 36 4
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VA: VMSUMMBM 37 4
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VA: VMSUMUHM 38 4
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VA: VMSUMUHS 39 4
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VA: VMSUMSHM 40 4
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VA: VMSUMSHS 41 4
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VA: VSEL 42 4
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VA: VPERM 43 4
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VA: VSLDOI 44 4
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VA: VMADDFP 46 4
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VA: VNMSUBFP 47 4
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VX: VADDUBM 0 4
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VX: VADDUHM 64 4
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VX: VADDUWM 128 4
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VX: VADDCUW 384 4
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VX: VADDUBS 512 4
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VX: VADDUHS 576 4
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VX: VADDUWS 640 4
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VX: VADDSBS 768 4
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VX: VADDSHS 832 4
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VX: VADDSWS 896 4
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VX: VSUBUBM 1024 4
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VX: VSUBUHM 1088 4
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VX: VSUBUWM 1152 4
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VX: VSUBCUW 1408 4
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VX: VSUBUBS 1536 4
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VX: VSUBUHS 1600 4
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VX: VSUBUWS 1664 4
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VX: VSUBSBS 1792 4
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VX: VSUBSHS 1856 4
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VX: VSUBSWS 1920 4
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VX: VMAXUB 2 4
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VX: VMAXUH 66 4
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VX: VMAXUW 130 4
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VX: VMAXSB 258 4
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VX: VMAXSH 322 4
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VX: VMAXSW 386 4
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VX: VMINUB 514 4
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VX: VMINUH 578 4
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VX: VMINUW 642 4
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VX: VMINSB 770 4
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VX: VMINSH 834 4
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VX: VMINSW 898 4
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VX: VAVGUB 1026 4
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VX: VAVGUH 1090 4
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VX: VAVGUW 1154 4
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VX: VAVGSB 1282 4
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VX: VAVGSH 1346 4
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VX: VAVGSW 1410 4
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VX: VRLB 4 4
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VX: VRLH 68 4
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VX: VRLW 132 4
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VX: VSLB 260 4
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VX: VSLH 324 4
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VX: VSLW 388 4
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VX: VSL 452 4
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VX: VSRB 516 4
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VX: VSRH 580 4
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VX: VSRW 644 4
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VX: VSR 708 4
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VX: VSRAB 772 4
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VX: VSRAH 836 4
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VX: VSRAW 900 4
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VX: VAND 1028 4
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VX: VANDC 1092 4
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VX: VOR 1156 4
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VX: VNOR 1284 4
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VX: VXOR 1220 4
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VXD: MFVSCR 1540 4
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VXB: MTVSCR 1604 4
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VX: VMULOUB 8 4
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VX: VMULOUH 72 4
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VX: VMULOSB 264 4
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VX: VMULOSH 328 4
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VX: VMULEUB 520 4
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VX: VMULEUH 584 4
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VX: VMULESB 776 4
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VX: VMULESH 840 4
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VX: VSUM4UBS 1544 4
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VX: VSUM4SBS 1800 4
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VX: VSUM4SHS 1608 4
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VX: VSUM2SWS 1672 4
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VX: VSUMSWS 1928 4
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VX: VADDFP 10 4
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VX: VSUBFP 74 4
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VXDB: VREFP 266 4
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VXDB: VRSQRTEFP 330 4
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VXDB: VEXPTEFP 394 4
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VXDB: VLOGEFP 458 4
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VXDB: VRFIN 522 4
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VXDB: VRFIZ 586 4
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VXDB: VRFIP 650 4
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VXDB: VRFIM 714 4
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VX: VCFUX 778 4
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VX: VCFSX 842 4
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VX: VCTUXS 906 4
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VX: VCTSXS 970 4
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VX: VMAXFP 1034 4
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VX: VMINFP 1098 4
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VX: VMRGHB 12 4
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VX: VMRGHH 76 4
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VX: VMRGHW 140 4
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VX: VMRGLB 268 4
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VX: VMRGLH 332 4
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VX: VMRGLW 396 4
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VX: VSPLTB 524 4
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VX: VSPLTH 588 4
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VX: VSPLTW 652 4
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VXA: VSPLTISB 780 4
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VXA: VSPLTISH 844 4
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VXA: VSPLTISW 908 4
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VX: VSLO 1036 4
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VX: VSRO 1100 4
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VX: VPKUHUM 14 4
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VX: VPKUWUM 78 4
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VX: VPKUHUS 142 4
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VX: VPKUWUS 206 4
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VX: VPKSHUS 270 4
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VX: VPKSWUS 334 4
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VX: VPKSHSS 398 4
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VX: VPKSWSS 462 4
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VX: VPKPX 782 4
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VXDB: VUPKHSB 526 4
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VXDB: VUPKHSH 590 4
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VXDB: VUPKLSB 654 4
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VXDB: VUPKLSH 718 4
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VXDB: VUPKHPX 846 4
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VXDB: VUPKLPX 974 4
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: -T ( strm a b -- strm-t a b ) [ 16 bitor ] 2dip ;
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XD: DST 0 342 31
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: DSTT ( strm a b -- ) -T DST ;
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XD: DSTST 0 374 31
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: DSTSTT ( strm a b -- ) -T DSTST ;
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XD: (DSS) 0 822 31
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: DSS ( strm -- ) 0 0 (DSS) ;
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: DSSALL ( -- ) 16 0 0 (DSS) ;
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XD: LVEBX 0 7 31
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XD: LVEHX 0 39 31
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XD: LVEWX 0 71 31
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XD: LVSL 0 6 31
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XD: LVSR 0 38 31
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XD: LVX 0 103 31
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XD: LVXL 0 359 31
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XD: STVEBX 0 135 31
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XD: STVEHX 0 167 31
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XD: STVEWX 0 199 31
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XD: STVX 0 231 31
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XD: STVXL 0 487 31
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VXR: VCMPBFP 0 966 4
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VXR: VCMPEQFP 0 198 4
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VXR: VCMPEQUB 0 6 4
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VXR: VCMPEQUH 0 70 4
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VXR: VCMPEQUW 0 134 4
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VXR: VCMPGEFP 0 454 4
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VXR: VCMPGTFP 0 710 4
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VXR: VCMPGTSB 0 774 4
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VXR: VCMPGTSH 0 838 4
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VXR: VCMPGTSW 0 902 4
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VXR: VCMPGTUB 0 518 4
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VXR: VCMPGTUH 0 582 4
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VXR: VCMPGTUW 0 646 4
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VXR: VCMPBFP. 1 966 4
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VXR: VCMPEQFP. 1 198 4
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VXR: VCMPEQUB. 1 6 4
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VXR: VCMPEQUH. 1 70 4
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VXR: VCMPEQUW. 1 134 4
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VXR: VCMPGEFP. 1 454 4
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VXR: VCMPGTFP. 1 710 4
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VXR: VCMPGTSB. 1 774 4
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VXR: VCMPGTSH. 1 838 4
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VXR: VCMPGTSW. 1 902 4
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VXR: VCMPGTUB. 1 518 4
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VXR: VCMPGTUH. 1 582 4
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VXR: VCMPGTUW. 1 646 4
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