200 lines
6.0 KiB
Factor
200 lines
6.0 KiB
Factor
USING: accessors arrays classes compiler.cfg
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compiler.cfg.debugger compiler.cfg.instructions
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compiler.cfg.linear-scan.debugger
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compiler.cfg.linear-scan.live-intervals
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compiler.cfg.linear-scan.numbering
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compiler.cfg.linear-scan.resolve compiler.cfg.predecessors
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compiler.cfg.registers compiler.cfg.rpo cpu.architecture kernel
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namespaces tools.test vectors ;
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IN: compiler.cfg.linear-scan.resolve.tests
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[ { 1 2 3 4 5 6 } ] [
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{ 3 4 } V{ 1 2 } clone [ { 5 6 } 3append-here ] keep >array
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] unit-test
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V{
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T{ ##peek f V int-regs 0 D 0 }
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T{ ##branch }
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} 0 test-bb
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V{
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T{ ##replace f V int-regs 0 D 1 }
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T{ ##return }
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} 1 test-bb
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1 get 1vector 0 get (>>successors)
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cfg new 0 get >>entry
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compute-predecessors
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dup reverse-post-order number-instructions
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drop
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CONSTANT: test-live-interval-1
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T{ live-interval
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{ start 0 }
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{ end 6 }
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{ uses V{ 0 6 } }
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{ ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
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{ spill-to 0 }
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{ vreg V int-regs 0 }
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}
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[ f ] [
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0 get test-live-interval-1 spill-to
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] unit-test
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[ 0 ] [
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1 get test-live-interval-1 spill-to
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] unit-test
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CONSTANT: test-live-interval-2
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T{ live-interval
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{ start 0 }
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{ end 6 }
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{ uses V{ 0 6 } }
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{ ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
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{ reload-from 0 }
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{ vreg V int-regs 0 }
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}
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[ 0 ] [
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0 get test-live-interval-2 reload-from
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] unit-test
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[ f ] [
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1 get test-live-interval-2 reload-from
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] unit-test
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[
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{
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T{ _copy { dst 5 } { src 4 } { class int-regs } }
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T{ _spill { src 0 } { class int-regs } { n 6 } }
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T{ _copy { dst 0 } { src 1 } { class int-regs } }
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T{ _reload { dst 1 } { class int-regs } { n 6 } }
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T{ _spill { src 0 } { class float-regs } { n 7 } }
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T{ _copy { dst 0 } { src 1 } { class float-regs } }
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T{ _reload { dst 1 } { class float-regs } { n 7 } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 1 } { to 0 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 1 } { reg-class float-regs } }
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T{ register->register { from 1 } { to 0 } { reg-class float-regs } }
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T{ register->register { from 4 } { to 5 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _spill { src 0 } { class int-regs } { n 3 } }
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T{ _copy { dst 0 } { src 2 } { class int-regs } }
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T{ _copy { dst 2 } { src 1 } { class int-regs } }
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T{ _reload { dst 1 } { class int-regs } { n 3 } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
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T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _spill { src 0 } { class int-regs } { n 3 } }
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T{ _copy { dst 0 } { src 2 } { class int-regs } }
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T{ _copy { dst 2 } { src 1 } { class int-regs } }
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T{ _reload { dst 1 } { class int-regs } { n 3 } }
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}
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] [
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{
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T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
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T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{ }
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] [
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{
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T{ register->register { from 4 } { to 4 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{ T{ _spill { src 4 } { class int-regs } { n 4 } } }
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] [
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{
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T{ register->memory { from 4 } { to 4 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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T{ _copy { dst 0 } { src 3 } { class int-regs } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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T{ _spill { src 3 } { class int-regs } { n 5 } }
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T{ _copy { dst 4 } { src 0 } { class int-regs } }
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T{ _copy { dst 3 } { src 4 } { class int-regs } }
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T{ _reload { dst 0 } { class int-regs } { n 5 } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
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T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
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T{ register->register { from 4 } { to 3 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 4 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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[
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{
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T{ _copy { dst 2 } { src 0 } { class int-regs } }
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T{ _copy { dst 9 } { src 1 } { class int-regs } }
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T{ _copy { dst 1 } { src 0 } { class int-regs } }
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T{ _spill { src 3 } { class int-regs } { n 10 } }
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T{ _copy { dst 4 } { src 0 } { class int-regs } }
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T{ _copy { dst 3 } { src 4 } { class int-regs } }
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T{ _reload { dst 0 } { class int-regs } { n 10 } }
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}
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] [
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{
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T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
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T{ register->register { from 1 } { to 9 } { reg-class int-regs } }
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T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
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T{ register->register { from 4 } { to 3 } { reg-class int-regs } }
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T{ register->register { from 0 } { to 4 } { reg-class int-regs } }
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} mapping-instructions
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] unit-test
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