210 lines
4.4 KiB
Factor
210 lines
4.4 KiB
Factor
! Copyright (C) 2005, 2008 Slava Pestov.
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! See http://factorcode.org/license.txt for BSD license.
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USING: compiler.codegen.fixup kernel namespaces words
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io.binary math math.order cpu.ppc.assembler.backend ;
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IN: cpu.ppc.assembler
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! See the Motorola or IBM documentation for details. The opcode
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! names are standard, and the operand order is the same as in
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! the docs, except a few differences, namely, in IBM/Motorola
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! assembler syntax, loads and stores are written like:
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!
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! stw r14,10(r15)
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!
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! In Factor, we write:
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!
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! 14 15 10 STW
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! D-form
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D: ADDI 14
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D: ADDIC 12
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D: ADDIC. 13
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D: ADDIS 15
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D: CMPI 11
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D: CMPLI 10
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D: LBZ 34
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D: LBZU 35
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D: LFD 50
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D: LFDU 51
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D: LFS 48
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D: LFSU 49
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D: LHA 42
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D: LHAU 43
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D: LHZ 40
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D: LHZU 41
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D: LWZ 32
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D: LWZU 33
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D: MULI 7
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D: MULLI 7
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D: STB 38
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D: STBU 39
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D: STFD 54
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D: STFDU 55
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D: STFS 52
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D: STFSU 53
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D: STH 44
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D: STHU 45
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D: STW 36
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D: STWU 37
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! SD-form
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SD: ANDI 28
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SD: ANDIS 29
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SD: ORI 24
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SD: ORIS 25
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SD: XORI 26
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SD: XORIS 27
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! X-form
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X: AND 0 28 31
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X: AND. 1 28 31
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X: CMP 0 0 31
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X: CMPL 0 32 31
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X: EQV 0 284 31
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X: EQV. 1 284 31
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X: FCMPO 0 32 63
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X: FCMPU 0 0 63
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X: LBZUX 0 119 31
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X: LBZX 0 87 31
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X: LHAUX 0 375 31
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X: LHAX 0 343 31
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X: LHZUX 0 311 31
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X: LHZX 0 279 31
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X: LWZUX 0 55 31
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X: LWZX 0 23 31
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X: NAND 0 476 31
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X: NAND. 1 476 31
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X: NOR 0 124 31
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X: NOR. 1 124 31
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X: OR 0 444 31
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X: OR. 1 444 31
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X: ORC 0 412 31
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X: ORC. 1 412 31
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X: SLW 0 24 31
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X: SLW. 1 24 31
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X: SRAW 0 792 31
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X: SRAW. 1 792 31
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X: SRAWI 0 824 31
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X: SRW 0 536 31
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X: SRW. 1 536 31
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X: STBUX 0 247 31
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X: STBX 0 215 31
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X: STHUX 0 439 31
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X: STHX 0 407 31
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X: STWUX 0 183 31
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X: STWX 0 151 31
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X: XOR 0 316 31
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X: XOR. 1 316 31
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X1: EXTSB 0 954 31
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X1: EXTSB. 1 954 31
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: FMR ( a s -- ) [ 0 ] 2dip 72 0 63 x-insn ;
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: FMR. ( a s -- ) [ 0 ] 2dip 72 1 63 x-insn ;
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: FCTIWZ ( a s -- ) [ 0 ] 2dip 0 15 63 x-insn ;
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: FCTIWZ. ( a s -- ) [ 0 ] 2dip 1 15 63 x-insn ;
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! XO-form
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XO: ADD 0 0 266 31
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XO: ADD. 0 1 266 31
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XO: ADDC 0 0 10 31
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XO: ADDC. 0 1 10 31
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XO: ADDCO 1 0 10 31
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XO: ADDCO. 1 1 10 31
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XO: ADDE 0 0 138 31
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XO: ADDE. 0 1 138 31
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XO: ADDEO 1 0 138 31
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XO: ADDEO. 1 1 138 31
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XO: ADDO 1 0 266 31
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XO: ADDO. 1 1 266 31
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XO: DIVW 0 0 491 31
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XO: DIVW. 0 1 491 31
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XO: DIVWO 1 0 491 31
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XO: DIVWO. 1 1 491 31
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XO: DIVWU 0 0 459 31
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XO: DIVWU. 0 1 459 31
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XO: DIVWUO 1 0 459 31
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XO: DIVWUO. 1 1 459 31
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XO: MULHW 0 0 75 31
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XO: MULHW. 0 1 75 31
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XO: MULHWU 0 0 11 31
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XO: MULHWU. 0 1 11 31
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XO: MULLW 0 0 235 31
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XO: MULLW. 0 1 235 31
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XO: MULLWO 1 0 235 31
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XO: MULLWO. 1 1 235 31
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XO: SUBF 0 0 40 31
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XO: SUBF. 0 1 40 31
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XO: SUBFC 0 0 8 31
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XO: SUBFC. 0 1 8 31
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XO: SUBFCO 1 0 8 31
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XO: SUBFCO. 1 1 8 31
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XO: SUBFE 0 0 136 31
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XO: SUBFE. 0 1 136 31
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XO: SUBFEO 1 0 136 31
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XO: SUBFEO. 1 1 136 31
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XO: SUBFO 1 0 40 31
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XO: SUBFO. 1 1 40 31
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XO1: NEG 0 0 104 31
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XO1: NEG. 0 1 104 31
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XO1: NEGO 1 0 104 31
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XO1: NEGO. 1 1 104 31
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! A-form
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: RLWINM ( d a b c xo -- ) 0 21 a-insn ;
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: RLWINM. ( d a b c xo -- ) 1 21 a-insn ;
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: FADD ( d a b -- ) 0 21 0 63 a-insn ;
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: FADD. ( d a b -- ) 0 21 1 63 a-insn ;
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: FSUB ( d a b -- ) 0 20 0 63 a-insn ;
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: FSUB. ( d a b -- ) 0 20 1 63 a-insn ;
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: FMUL ( d a c -- ) 0 swap 25 0 63 a-insn ;
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: FMUL. ( d a c -- ) 0 swap 25 1 63 a-insn ;
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: FDIV ( d a b -- ) 0 18 0 63 a-insn ;
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: FDIV. ( d a b -- ) 0 18 1 63 a-insn ;
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: FSQRT ( d b -- ) 0 swap 0 22 0 63 a-insn ;
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: FSQRT. ( d b -- ) 0 swap 0 22 1 63 a-insn ;
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! Branches
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: B ( dest -- ) 0 0 (B) ;
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: BL ( dest -- ) 0 1 (B) ;
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BC: LT 12 0
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BC: GE 4 0
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BC: GT 12 1
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BC: LE 4 1
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BC: EQ 12 2
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BC: NE 4 2
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BC: O 12 3
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BC: NO 4 3
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B: CLR 0 8 0 0 19
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B: CLRL 0 8 0 1 19
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B: CCTR 0 264 0 0 19
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: BLR ( -- ) 20 BCLR ;
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: BLRL ( -- ) 20 BCLRL ;
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: BCTR ( -- ) 20 BCCTR ;
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! Special registers
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MFSPR: XER 1
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MFSPR: LR 8
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MFSPR: CTR 9
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MTSPR: XER 1
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MTSPR: LR 8
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MTSPR: CTR 9
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! Pseudo-instructions
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: LI ( value dst -- ) 0 rot ADDI ; inline
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: SUBI ( dst src1 src2 -- ) neg ADDI ; inline
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: LIS ( value dst -- ) 0 rot ADDIS ; inline
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: SUBIC ( dst src1 src2 -- ) neg ADDIC ; inline
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: SUBIC. ( dst src1 src2 -- ) neg ADDIC. ; inline
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: NOT ( dst src -- ) dup NOR ; inline
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: NOT. ( dst src -- ) dup NOR. ; inline
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: MR ( dst src -- ) dup OR ; inline
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: MR. ( dst src -- ) dup OR. ; inline
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: (SLWI) ( d a b -- d a b x y ) 0 31 pick - ; inline
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: SLWI ( d a b -- ) (SLWI) RLWINM ;
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: SLWI. ( d a b -- ) (SLWI) RLWINM. ;
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: (SRWI) ( d a b -- d a b x y ) 32 over - swap 31 ; inline
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: SRWI ( d a b -- ) (SRWI) RLWINM ;
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: SRWI. ( d a b -- ) (SRWI) RLWINM. ;
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: LOAD32 ( n r -- ) [ w>h/h ] dip tuck LIS dup rot ORI ;
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: immediate? ( n -- ? ) HEX: -8000 HEX: 7fff between? ;
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: LOAD ( n r -- ) over immediate? [ LI ] [ LOAD32 ] if ;
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