590 lines
14 KiB
Factor
590 lines
14 KiB
Factor
USING: tools.test random sorting sequences hashtables assocs
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kernel fry arrays splitting namespaces math accessors vectors locals
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math.order grouping strings strings.private classes layouts
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cpu.architecture
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compiler.cfg
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compiler.cfg.optimizer
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compiler.cfg.instructions
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compiler.cfg.registers
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compiler.cfg.predecessors
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compiler.cfg.rpo
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compiler.cfg.debugger
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compiler.cfg.def-use
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compiler.cfg.comparisons
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compiler.cfg.ssa.destruction.leaders
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compiler.cfg.linear-scan
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compiler.cfg.linear-scan.allocation
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compiler.cfg.linear-scan.allocation.state
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compiler.cfg.linear-scan.allocation.splitting
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compiler.cfg.linear-scan.allocation.spilling
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compiler.cfg.linear-scan.live-intervals
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compiler.cfg.linear-scan.numbering
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compiler.cfg.linear-scan.ranges
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compiler.cfg.linear-scan.debugger
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compiler.cfg.utilities ;
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IN: compiler.cfg.linear-scan.tests
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check-allocation? on
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check-numbering? on
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! Live interval calculation
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: test-live-intervals ( -- )
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! A value is defined and never used; make sure it has the right
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! live range
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{
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T{ ##load-integer f 1 0 }
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T{ ##replace-imm f D: 0 "hi" }
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T{ ##branch }
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} insns>cfg
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[ cfg set ] [ number-instructions ] [ compute-live-intervals ] tri
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drop ;
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{ } [
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H{
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{ 1 int-rep }
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} representations set
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H{
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{ 1 1 }
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} leader-map set
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test-live-intervals
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] unit-test
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{ 0 0 } [
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1 live-intervals get at ranges>> ranges-endpoints
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] unit-test
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! Live interval splitting
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{ } insns>cfg [ stack-frame>> 4 >>spill-area-align drop ] keep cfg set
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H{ } spill-slots set
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H{
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{ 1 float-rep }
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{ 2 float-rep }
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{ 3 float-rep }
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} representations set
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: clean-up-split ( a b -- a b )
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[ dup [ [ >vector ] change-uses [ >vector ] change-ranges ] when ] bi@ ;
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } } }
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{ ranges V{ { 0 2 } } }
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{ spill-to T{ spill-slot f 0 } }
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{ spill-rep float-rep }
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}
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ { 5 5 } } }
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{ reload-from T{ spill-slot f 0 } }
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{ reload-rep float-rep }
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}
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} [
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T{ live-interval-state
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{ vreg 1 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 1 f float-rep }
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T{ vreg-use f 5 f float-rep }
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}
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}
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{ ranges V{ { 0 5 } } }
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} 2 split-for-spill
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clean-up-split
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] unit-test
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{
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f
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T{ live-interval-state
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{ vreg 2 }
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{ uses V{ T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ { 1 5 } } }
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{ reload-from T{ spill-slot f 4 } }
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{ reload-rep float-rep }
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}
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} [
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T{ live-interval-state
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{ vreg 2 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 1 f float-rep }
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T{ vreg-use f 5 f float-rep }
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}
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}
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{ ranges V{ { 0 5 } } }
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} 0 split-for-spill
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clean-up-split
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] unit-test
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{
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T{ live-interval-state
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{ vreg 3 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } } }
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{ ranges V{ { 0 2 } } }
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{ spill-to T{ spill-slot f 8 } }
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{ spill-rep float-rep }
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}
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f
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} [
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T{ live-interval-state
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{ vreg 3 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 1 f float-rep }
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T{ vreg-use f 5 f float-rep }
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}
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}
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{ ranges V{ { 0 5 } } }
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} 5 split-for-spill
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clean-up-split
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] unit-test
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{
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T{ live-interval-state
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{ vreg 4 }
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{ uses V{ T{ vreg-use f 0 float-rep f } } }
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{ ranges V{ { 0 1 } } }
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{ spill-to T{ spill-slot f 12 } }
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{ spill-rep float-rep }
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}
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T{ live-interval-state
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{ vreg 4 }
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{ uses V{ T{ vreg-use f 20 f float-rep } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ { 20 30 } } }
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{ reload-from T{ spill-slot f 12 } }
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{ reload-rep float-rep }
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}
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} [
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T{ live-interval-state
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{ vreg 4 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 20 f float-rep }
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T{ vreg-use f 30 f float-rep }
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}
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}
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{ ranges V{ { 0 8 } { 10 18 } { 20 30 } } }
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} 10 split-for-spill
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clean-up-split
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] unit-test
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! Don't insert reload if first usage is a def
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{
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T{ live-interval-state
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{ vreg 5 }
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{ uses V{ T{ vreg-use f 0 float-rep f } } }
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{ ranges V{ { 0 1 } } }
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{ spill-to T{ spill-slot f 16 } }
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{ spill-rep float-rep }
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}
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T{ live-interval-state
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{ vreg 5 }
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{ uses V{ T{ vreg-use f 20 float-rep f } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ { 20 30 } } }
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}
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} [
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T{ live-interval-state
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{ vreg 5 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 20 float-rep f }
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T{ vreg-use f 30 f float-rep }
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}
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}
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{ ranges V{ { 0 8 } { 10 18 } { 20 30 } } }
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} 10 split-for-spill
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clean-up-split
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] unit-test
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! Multiple representations
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{
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T{ live-interval-state
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{ vreg 6 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 10 double-rep float-rep } } }
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{ ranges V{ { 0 11 } } }
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{ spill-to T{ spill-slot f 24 } }
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{ spill-rep double-rep }
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}
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T{ live-interval-state
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{ vreg 6 }
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{ uses V{ T{ vreg-use f 20 f double-rep } } }
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{ ranges V{ { 20 20 } } }
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{ reload-from T{ spill-slot f 24 } }
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{ reload-rep double-rep }
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}
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} [
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T{ live-interval-state
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{ vreg 6 }
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{ uses
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V{
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T{ vreg-use f 0 float-rep f }
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T{ vreg-use f 10 double-rep float-rep }
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T{ vreg-use f 20 f double-rep }
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}
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}
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{ ranges V{ { 0 20 } } }
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} 15 split-for-spill
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clean-up-split
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] unit-test
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{
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f
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T{ live-interval-state
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{ vreg 7 }
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{ ranges V{ { 8 8 } } }
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{ uses V{ T{ vreg-use f 8 int-rep } } }
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}
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} [
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T{ live-interval-state
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{ vreg 7 }
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{ ranges V{ { 4 8 } } }
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{ uses V{ T{ vreg-use f 8 int-rep } } }
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} 4 split-for-spill
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clean-up-split
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] unit-test
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! trim-before-ranges, trim-after-ranges
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{
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T{ live-interval-state
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{ vreg 8 }
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{ ranges V{ { 0 3 } } }
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{ uses V{ T{ vreg-use f 0 f int-rep } T{ vreg-use f 2 f int-rep } } }
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{ spill-to T{ spill-slot f 32 } }
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{ spill-rep int-rep }
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}
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T{ live-interval-state
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{ vreg 8 }
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{ ranges V{ { 14 16 } } }
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{ uses V{ T{ vreg-use f 14 f int-rep } } }
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{ reload-from T{ spill-slot f 32 } }
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{ reload-rep int-rep }
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}
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} [
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T{ live-interval-state
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{ vreg 8 }
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{ ranges V{ { 0 4 } { 6 10 } { 12 16 } } }
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{ uses
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V{
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T{ vreg-use f 0 f int-rep }
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T{ vreg-use f 2 f int-rep }
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T{ vreg-use f 14 f int-rep } }
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}
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} 8 split-for-spill
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clean-up-split
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] unit-test
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H{
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{ 1 int-rep }
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{ 2 int-rep }
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{ 3 int-rep }
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} representations set
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{
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{
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3
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10
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}
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} [
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H{
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{ int-regs
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V{
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T{ live-interval-state
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{ vreg 1 }
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{ reg 1 }
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{ ranges V{ { 1 15 } } }
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{ uses
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V{
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T{ vreg-use f 1 int-rep f }
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T{ vreg-use f 3 f int-rep }
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T{ vreg-use f 7 f int-rep }
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T{ vreg-use f 10 f int-rep }
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T{ vreg-use f 15 f int-rep }
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}
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}
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}
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T{ live-interval-state
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{ vreg 2 }
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{ reg 2 }
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{ ranges V{ { 3 8 } } }
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{ uses
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V{
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T{ vreg-use f 3 int-rep f }
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T{ vreg-use f 4 f int-rep }
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T{ vreg-use f 8 f int-rep }
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}
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}
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}
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T{ live-interval-state
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{ vreg 3 }
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{ reg 3 }
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{ ranges V{ { 3 10 } } }
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{ uses V{ T{ vreg-use f 3 int-rep f } T{ vreg-use f 10 f int-rep } } }
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}
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}
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}
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} active-intervals set
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H{ } inactive-intervals set
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T{ live-interval-state
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{ vreg 1 }
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{ ranges V{ { 5 5 } } }
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{ uses V{ T{ vreg-use f 5 int-rep f } } }
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}
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spill-status
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] unit-test
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{
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{
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1
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1/0.
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}
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} [
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H{
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{ int-regs
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V{
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T{ live-interval-state
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{ vreg 1 }
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{ reg 1 }
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{ ranges V{ { 1 15 } } }
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{ uses V{ T{ vreg-use f 1 int-rep f } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ reg 2 }
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{ uses V{ T{ vreg-use f 3 int-rep f } T{ vreg-use f 8 f int-rep } } }
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}
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}
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}
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} active-intervals set
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H{ } inactive-intervals set
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T{ live-interval-state
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{ vreg 3 }
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{ ranges V{ { 5 5 } } }
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{ uses V{ T{ vreg-use f 5 int-rep f } } }
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}
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spill-status
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] unit-test
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H{ { 1 int-rep } { 2 int-rep } } representations set
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ { 0 100 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } } }
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{ ranges V{ { 0 10 } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ uses V{ T{ vreg-use f 11 int-rep f } T{ vreg-use f 20 f int-rep } } }
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{ ranges V{ { 11 20 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ { 0 100 } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 60 f int-rep } } }
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{ ranges V{ { 30 60 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ { 0 100 } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 200 f int-rep } } }
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{ ranges V{ { 30 200 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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[
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ { 0 100 } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ { 30 100 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] must-fail
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! Problem with spilling intervals with no more usages after the spill location
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H{
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{ 1 int-rep }
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{ 2 int-rep }
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{ 3 int-rep }
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{ 4 int-rep }
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{ 5 int-rep }
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} representations set
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses
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V{
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T{ vreg-use f 0 int-rep f }
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T{ vreg-use f 10 f int-rep }
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T{ vreg-use f 20 f int-rep }
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}
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}
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{ ranges V{ { 0 2 } { 10 20 } } }
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}
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T{ live-interval-state
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{ vreg 2 }
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{ uses
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V{
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T{ vreg-use f 0 int-rep f }
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T{ vreg-use f 10 f int-rep }
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T{ vreg-use f 20 f int-rep }
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}
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}
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{ ranges V{ { 0 2 } { 10 20 } } }
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}
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T{ live-interval-state
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{ vreg 3 }
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{ uses V{ T{ vreg-use f 6 int-rep f } } }
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{ ranges V{ { 4 8 } } }
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}
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T{ live-interval-state
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{ vreg 4 }
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
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{ ranges V{ { 4 8 } } }
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}
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! This guy will invoke the 'spill partially available' code path
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T{ live-interval-state
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{ vreg 5 }
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
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{ ranges V{ { 4 8 } } }
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}
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}
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H{ { int-regs { "A" "B" } } }
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check-linear-scan
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] unit-test
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! Test spill-new code path
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{ } [
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{
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T{ live-interval-state
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{ vreg 1 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 6 f int-rep } T{ vreg-use f 10 f int-rep } } }
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{ ranges V{ { 0 10 } } }
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}
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! This guy will invoke the 'spill new' code path
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T{ live-interval-state
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{ vreg 5 }
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
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{ ranges V{ { 2 8 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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! register-status had problems because it used map>assoc where the sequence
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! had multiple keys
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H{
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{ 1 int-rep }
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{ 2 int-rep }
|
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{ 3 int-rep }
|
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{ 4 int-rep }
|
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} representations set
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{ { 0 10 } } [
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H{
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{ int-regs
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{
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T{ live-interval-state
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{ vreg 1 }
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{ reg 0 }
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{ ranges V{ { 0 2 } { 10 20 } } }
|
|
{ uses V{ 0 2 10 20 } }
|
|
}
|
|
|
|
T{ live-interval-state
|
|
{ vreg 2 }
|
|
{ reg 0 }
|
|
{ ranges V{ { 4 6 } { 30 40 } } }
|
|
{ uses V{ 4 6 30 40 } }
|
|
}
|
|
}
|
|
}
|
|
} inactive-intervals set
|
|
H{
|
|
{ int-regs
|
|
{
|
|
T{ live-interval-state
|
|
{ vreg 3 }
|
|
{ reg 1 }
|
|
{ ranges V{ { 0 40 } } }
|
|
{ uses V{ 0 40 } }
|
|
}
|
|
}
|
|
}
|
|
} active-intervals set
|
|
|
|
T{ live-interval-state
|
|
{ vreg 4 }
|
|
{ ranges V{ { 8 10 } } }
|
|
{ uses V{ T{ vreg-use f 8 int-rep f } T{ vreg-use f 10 f int-rep } } }
|
|
}
|
|
H{ { int-regs { 0 1 } } } register-status
|
|
] unit-test
|
|
|
|
{ t } [
|
|
T{ cfg { frame-pointer? f } } admissible-registers machine-registers =
|
|
] unit-test
|
|
|
|
{ f } [
|
|
T{ cfg { frame-pointer? t } } admissible-registers
|
|
int-regs of frame-reg swap member?
|
|
] unit-test
|