663 lines
17 KiB
Factor
663 lines
17 KiB
Factor
USING: tools.test random sorting sequences sets hashtables assocs
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kernel fry arrays splitting namespaces math accessors vectors locals
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math.order grouping strings strings.private classes layouts
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cpu.architecture
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compiler.cfg
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compiler.cfg.optimizer
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compiler.cfg.instructions
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compiler.cfg.registers
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compiler.cfg.predecessors
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compiler.cfg.rpo
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compiler.cfg.debugger
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compiler.cfg.def-use
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compiler.cfg.comparisons
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compiler.cfg.linear-scan
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compiler.cfg.linear-scan.numbering
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compiler.cfg.linear-scan.live-intervals
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compiler.cfg.linear-scan.allocation
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compiler.cfg.linear-scan.allocation.state
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compiler.cfg.linear-scan.allocation.splitting
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compiler.cfg.linear-scan.allocation.spilling
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compiler.cfg.linear-scan.debugger ;
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FROM: namespaces => set ;
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IN: compiler.cfg.linear-scan.tests
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check-allocation? on
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check-numbering? on
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[
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{ T{ live-range f 1 10 } T{ live-range f 15 15 } }
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{ T{ live-range f 16 20 } }
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] [
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{
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T{ live-range f 1 10 }
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T{ live-range f 15 20 }
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} 15 split-ranges
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] unit-test
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[
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{ T{ live-range f 1 10 } T{ live-range f 15 16 } }
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{ T{ live-range f 17 20 } }
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] [
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{
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T{ live-range f 1 10 }
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T{ live-range f 15 20 }
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} 16 split-ranges
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] unit-test
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[
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{ T{ live-range f 1 10 } }
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{ T{ live-range f 15 20 } }
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] [
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{
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T{ live-range f 1 10 }
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T{ live-range f 15 20 }
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} 12 split-ranges
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] unit-test
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[
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{ T{ live-range f 1 10 } T{ live-range f 15 17 } }
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{ T{ live-range f 18 20 } }
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] [
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{
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T{ live-range f 1 10 }
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T{ live-range f 15 20 }
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} 17 split-ranges
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] unit-test
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[
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{ T{ live-range f 1 10 } } 0 split-ranges
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] must-fail
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[
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{ T{ live-range f 0 0 } }
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{ T{ live-range f 1 5 } }
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] [
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{ T{ live-range f 0 5 } } 0 split-ranges
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] unit-test
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cfg new 0 >>spill-area-size cfg set
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H{ } spill-slots set
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H{
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{ 1 float-rep }
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{ 2 float-rep }
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{ 3 float-rep }
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} representations set
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[
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 2 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } } }
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{ ranges V{ T{ live-range f 0 2 } } }
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{ spill-to T{ spill-slot f 0 } }
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{ spill-rep float-rep }
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}
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ T{ live-range f 5 5 } } }
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{ reload-from T{ spill-slot f 0 } }
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{ reload-rep float-rep }
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}
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] [
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ T{ live-range f 0 5 } } }
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} 2 split-for-spill
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] unit-test
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[
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f
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T{ live-interval
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{ vreg 2 }
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{ reg-class float-regs }
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{ start 1 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ T{ live-range f 1 5 } } }
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{ reload-from T{ spill-slot f 4 } }
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{ reload-rep float-rep }
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}
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] [
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T{ live-interval
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{ vreg 2 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 1 f float-rep } T{ vreg-use f 5 f float-rep } } }
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{ ranges V{ T{ live-range f 0 5 } } }
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} 0 split-for-spill
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] unit-test
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[
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 1 }
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{ uses V{ T{ vreg-use f 0 float-rep f } } }
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{ ranges V{ T{ live-range f 0 1 } } }
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{ spill-to T{ spill-slot f 8 } }
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{ spill-rep float-rep }
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 20 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 20 f float-rep } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ T{ live-range f 20 30 } } }
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{ reload-from T{ spill-slot f 8 } }
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{ reload-rep float-rep }
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}
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] [
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 20 f float-rep } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ T{ live-range f 0 8 } T{ live-range f 10 18 } T{ live-range f 20 30 } } }
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} 10 split-for-spill
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] unit-test
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! Don't insert reload if first usage is a def
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[
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T{ live-interval
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{ vreg 4 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 1 }
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{ uses V{ T{ vreg-use f 0 float-rep f } } }
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{ ranges V{ T{ live-range f 0 1 } } }
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{ spill-to T{ spill-slot f 12 } }
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{ spill-rep float-rep }
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}
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T{ live-interval
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{ vreg 4 }
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{ reg-class float-regs }
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{ start 20 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 20 float-rep f } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ T{ live-range f 20 30 } } }
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}
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] [
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T{ live-interval
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{ vreg 4 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 20 float-rep f } T{ vreg-use f 30 f float-rep } } }
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{ ranges V{ T{ live-range f 0 8 } T{ live-range f 10 18 } T{ live-range f 20 30 } } }
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} 10 split-for-spill
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] unit-test
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! Multiple representations
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[
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T{ live-interval
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{ vreg 5 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 11 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 10 double-rep float-rep } } }
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{ ranges V{ T{ live-range f 0 11 } } }
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{ spill-to T{ spill-slot f 16 } }
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{ spill-rep double-rep }
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}
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T{ live-interval
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{ vreg 5 }
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{ reg-class float-regs }
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{ start 20 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 20 f double-rep } } }
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{ ranges V{ T{ live-range f 20 20 } } }
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{ reload-from T{ spill-slot f 16 } }
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{ reload-rep double-rep }
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}
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] [
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T{ live-interval
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{ vreg 5 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 0 float-rep f } T{ vreg-use f 10 double-rep float-rep } T{ vreg-use f 20 f double-rep } } }
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{ ranges V{ T{ live-range f 0 20 } } }
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} 15 split-for-spill
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] unit-test
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H{
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{ 1 int-rep }
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{ 2 int-rep }
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{ 3 int-rep }
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} representations set
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[
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{
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3
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10
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}
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] [
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H{
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{ int-regs
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V{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ reg 1 }
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{ start 1 }
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{ end 15 }
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{ uses V{ T{ vreg-use f 1 int-rep f } T{ vreg-use f 3 f int-rep } T{ vreg-use f 7 f int-rep } T{ vreg-use f 10 f int-rep } T{ vreg-use f 15 f int-rep } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ reg 2 }
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{ start 3 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 3 int-rep f } T{ vreg-use f 4 f int-rep } T{ vreg-use f 8 f int-rep } } }
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ reg 3 }
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{ start 3 }
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{ end 10 }
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{ uses V{ T{ vreg-use f 3 int-rep f } T{ vreg-use f 10 f int-rep } } }
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}
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}
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}
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} active-intervals set
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H{ } inactive-intervals set
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 int-rep f } } }
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}
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spill-status
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] unit-test
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[
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{
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1
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1/0.
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}
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] [
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H{
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{ int-regs
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V{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ reg 1 }
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{ start 1 }
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{ end 15 }
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{ uses V{ T{ vreg-use f 1 int-rep f } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ reg 2 }
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{ start 3 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 3 int-rep f } T{ vreg-use f 8 f int-rep } } }
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}
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}
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}
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} active-intervals set
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H{ } inactive-intervals set
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 int-rep f } } }
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}
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spill-status
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] unit-test
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H{ { 1 int-rep } { 2 int-rep } } representations set
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[ ] [
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ T{ live-range f 0 100 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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[ ] [
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 10 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } } }
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{ ranges V{ T{ live-range f 0 10 } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 11 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 11 int-rep f } T{ vreg-use f 20 f int-rep } } }
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{ ranges V{ T{ live-range f 11 20 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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[ ] [
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ T{ live-range f 0 100 } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 60 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 60 f int-rep } } }
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{ ranges V{ T{ live-range f 30 60 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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[ ] [
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ T{ live-range f 0 100 } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 200 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 200 f int-rep } } }
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{ ranges V{ T{ live-range f 30 200 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] unit-test
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[
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ T{ live-range f 0 100 } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 30 int-rep f } T{ vreg-use f 100 f int-rep } } }
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{ ranges V{ T{ live-range f 30 100 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
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] must-fail
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! Problem with spilling intervals with no more usages after the spill location
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H{
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{ 1 int-rep }
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{ 2 int-rep }
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{ 3 int-rep }
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{ 4 int-rep }
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{ 5 int-rep }
|
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} representations set
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[ ] [
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } T{ vreg-use f 20 f int-rep } } }
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{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 10 f int-rep } T{ vreg-use f 20 f int-rep } } }
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{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 6 int-rep f } } }
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{ ranges V{ T{ live-range f 4 8 } } }
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}
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T{ live-interval
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{ vreg 4 }
|
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
|
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{ ranges V{ T{ live-range f 4 8 } } }
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}
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|
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! This guy will invoke the 'spill partially available' code path
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T{ live-interval
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{ vreg 5 }
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
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{ ranges V{ T{ live-range f 4 8 } } }
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}
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}
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H{ { int-regs { "A" "B" } } }
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check-linear-scan
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] unit-test
|
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|
|
! Test spill-new code path
|
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|
[ ] [
|
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{
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T{ live-interval
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{ vreg 1 }
|
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{ reg-class int-regs }
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{ start 0 }
|
|
{ end 10 }
|
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{ uses V{ T{ vreg-use f 0 int-rep f } T{ vreg-use f 6 f int-rep } T{ vreg-use f 10 f int-rep } } }
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{ ranges V{ T{ live-range f 0 10 } } }
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}
|
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|
|
! This guy will invoke the 'spill new' code path
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T{ live-interval
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{ vreg 5 }
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{ reg-class int-regs }
|
|
{ start 2 }
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{ end 8 }
|
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{ uses V{ T{ vreg-use f 8 int-rep f } } }
|
|
{ ranges V{ T{ live-range f 2 8 } } }
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}
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}
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H{ { int-regs { "A" } } }
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check-linear-scan
|
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] unit-test
|
|
|
|
[ f ] [
|
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T{ live-range f 0 10 }
|
|
T{ live-range f 20 30 }
|
|
intersect-live-range
|
|
] unit-test
|
|
|
|
[ 10 ] [
|
|
T{ live-range f 0 10 }
|
|
T{ live-range f 10 30 }
|
|
intersect-live-range
|
|
] unit-test
|
|
|
|
[ 5 ] [
|
|
T{ live-range f 0 10 }
|
|
T{ live-range f 5 30 }
|
|
intersect-live-range
|
|
] unit-test
|
|
|
|
[ 5 ] [
|
|
T{ live-range f 5 30 }
|
|
T{ live-range f 0 10 }
|
|
intersect-live-range
|
|
] unit-test
|
|
|
|
[ 5 ] [
|
|
T{ live-range f 5 10 }
|
|
T{ live-range f 0 15 }
|
|
intersect-live-range
|
|
] unit-test
|
|
|
|
[ 50 ] [
|
|
{
|
|
T{ live-range f 0 10 }
|
|
T{ live-range f 20 30 }
|
|
T{ live-range f 40 50 }
|
|
}
|
|
{
|
|
T{ live-range f 11 15 }
|
|
T{ live-range f 31 35 }
|
|
T{ live-range f 50 55 }
|
|
}
|
|
intersect-live-ranges
|
|
] unit-test
|
|
|
|
[ f ] [
|
|
{
|
|
T{ live-range f 0 10 }
|
|
T{ live-range f 20 30 }
|
|
T{ live-range f 40 50 }
|
|
}
|
|
{
|
|
T{ live-range f 11 15 }
|
|
T{ live-range f 31 36 }
|
|
T{ live-range f 51 55 }
|
|
}
|
|
intersect-live-ranges
|
|
] unit-test
|
|
|
|
[ 5 ] [
|
|
T{ live-interval
|
|
{ start 0 }
|
|
{ reg-class int-regs }
|
|
{ end 10 }
|
|
{ uses { 0 10 } }
|
|
{ ranges V{ T{ live-range f 0 10 } } }
|
|
}
|
|
T{ live-interval
|
|
{ start 5 }
|
|
{ reg-class int-regs }
|
|
{ end 10 }
|
|
{ uses { 5 10 } }
|
|
{ ranges V{ T{ live-range f 5 10 } } }
|
|
}
|
|
relevant-ranges intersect-live-ranges
|
|
] unit-test
|
|
|
|
! register-status had problems because it used map>assoc where the sequence
|
|
! had multiple keys
|
|
H{
|
|
{ 1 int-rep }
|
|
{ 2 int-rep }
|
|
{ 3 int-rep }
|
|
{ 4 int-rep }
|
|
} representations set
|
|
|
|
[ { 0 10 } ] [
|
|
H{ { int-regs { 0 1 } } } registers set
|
|
H{
|
|
{ int-regs
|
|
{
|
|
T{ live-interval
|
|
{ vreg 1 }
|
|
{ reg-class int-regs }
|
|
{ start 0 }
|
|
{ end 20 }
|
|
{ reg 0 }
|
|
{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
|
|
{ uses V{ 0 2 10 20 } }
|
|
}
|
|
|
|
T{ live-interval
|
|
{ vreg 2 }
|
|
{ reg-class int-regs }
|
|
{ start 4 }
|
|
{ end 40 }
|
|
{ reg 0 }
|
|
{ ranges V{ T{ live-range f 4 6 } T{ live-range f 30 40 } } }
|
|
{ uses V{ 4 6 30 40 } }
|
|
}
|
|
}
|
|
}
|
|
} inactive-intervals set
|
|
H{
|
|
{ int-regs
|
|
{
|
|
T{ live-interval
|
|
{ vreg 3 }
|
|
{ reg-class int-regs }
|
|
{ start 0 }
|
|
{ end 40 }
|
|
{ reg 1 }
|
|
{ ranges V{ T{ live-range f 0 40 } } }
|
|
{ uses V{ 0 40 } }
|
|
}
|
|
}
|
|
}
|
|
} active-intervals set
|
|
|
|
T{ live-interval
|
|
{ vreg 4 }
|
|
{ reg-class int-regs }
|
|
{ start 8 }
|
|
{ end 10 }
|
|
{ ranges V{ T{ live-range f 8 10 } } }
|
|
{ uses V{ T{ vreg-use f 8 int-rep f } T{ vreg-use f 10 f int-rep } } }
|
|
}
|
|
register-status
|
|
] unit-test
|