Slava Pestov 3fb4fc1bde Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases		2009-07-16 23:50:48 -05:00
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32	Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint	2009-07-16 18:29:40 -05:00
64	Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint	2009-07-16 18:29:40 -05:00
assembler	cpu.x86.assembler: IMUL2 instruction was busted for immediate operands	2009-06-08 21:15:52 -05:00
features	cpu.x86.features: add RDTSC support. This is a new vocabulary with words: sse2? instruction-counter count-instructions	2009-05-31 15:02:14 -05:00
authors.txt	…
bootstrap.factor	Fix x86-64 backend	2009-05-07 16:58:18 -05:00
summary.txt	…
tags.txt	Add unportable tag	2008-11-06 09:29:21 -06:00
x86.factor	Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases	2009-07-16 23:50:48 -05:00