74 lines
1.4 KiB
ArmAsm
74 lines
1.4 KiB
ArmAsm
#if defined(__APPLE__)
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#define MANGLE(sym) _##sym
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#define XX @
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#else
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#define MANGLE(sym) sym
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#define XX ;
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#endif
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/* The returns and args are just for documentation */
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#define DEF(returns,symbol,args) .globl MANGLE(symbol) XX \
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MANGLE(symbol)
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/* Thanks to Joshua Grams for this code.
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On PowerPC processors, we must flush the instruction cache manually
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after writing to the code heap. */
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DEF(void,flush_icache,(void*, int)):
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/* compute number of cache lines to flush */
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add r4,r4,r3
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/* align addr to next lower cache line boundary */
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clrrwi r3,r3,5
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/* then n_lines = (len + 0x1f) / 0x20 */
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sub r4,r4,r3
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addi r4,r4,0x1f
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/* note '.' suffix */
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srwi. r4,r4,5
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/* if n_lines == 0, just return. */
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beqlr
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/* flush cache lines */
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mtctr r4
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/* for each line... */
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0: dcbf 0,r3
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sync
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icbi 0,r3
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addi r3,r3,0x20
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bdnz 0b
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/* finish up */
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sync
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isync
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blr
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DEF(void,get_ppc_fpu_env,(void*)):
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mffs f0
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stfd f0,0(r3)
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blr
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DEF(void,set_ppc_fpu_env,(const void*)):
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lfd f0,0(r3)
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mtfsf 0xff,f0
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blr
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DEF(void,get_ppc_vmx_env,(void*)):
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mfvscr v0
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subi r4,r1,16
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li r5,0xf
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andc r4,r4,r5
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stvxl v0,0,r4
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li r5,0xc
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lwzx r6,r5,r4
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stw r6,0(r3)
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blr
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DEF(void,set_ppc_vmx_env,(const void*)):
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subi r4,r1,16
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li r5,0xf
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andc r4,r4,r5
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li r5,0xc
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lwz r6,0(r3)
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stwx r6,r5,r4
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lvxl v0,0,r4
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mtvscr v0
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blr
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