353 lines
6.7 KiB
ArmAsm
353 lines
6.7 KiB
ArmAsm
/* Parts of this file were snarfed from SBCL src/runtime/ppc-assem.S, which is
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in the public domain. */
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#include "asm.h"
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#define DS_REG r13
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#define RS_REG r14
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#define VM_REG r15
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#define CALL_OR_JUMP_QUOT \
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lwz r11,12(r3) /* load quotation-xt slot */ XX \
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#define CALL_QUOT \
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CALL_OR_JUMP_QUOT XX \
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mtlr r11 /* prepare to call XT with quotation in r3 */ XX \
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blrl /* go */
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#define JUMP_QUOT \
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CALL_OR_JUMP_QUOT XX \
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mtctr r11 /* prepare to call XT with quotation in r3 */ XX \
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bctr /* go */
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#define PARAM_SIZE 32
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#define SAVED_INT_REGS_SIZE 96
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#define SAVED_FP_REGS_SIZE 144
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#define SAVED_V_REGS_SIZE 208
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#define FRAME (RESERVED_SIZE + PARAM_SIZE + SAVED_INT_REGS_SIZE + SAVED_FP_REGS_SIZE + SAVED_V_REGS_SIZE + 8)
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#if defined( __APPLE__)
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#define LR_SAVE 8
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#define RESERVED_SIZE 24
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#else
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#define LR_SAVE 4
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#define RESERVED_SIZE 8
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#endif
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#define SAVE_LR(reg) stw reg,(LR_SAVE + FRAME)(r1)
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#define LOAD_LR(reg) lwz reg,(LR_SAVE + FRAME)(r1)
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#define SAVE_AT(offset) (RESERVED_SIZE + PARAM_SIZE + 4 * offset)
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#define SAVE_INT(register,offset) stw register,SAVE_AT(offset)(r1)
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#define RESTORE_INT(register,offset) lwz register,SAVE_AT(offset)(r1)
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#define SAVE_FP(register,offset) stfd register,SAVE_AT(offset)(r1)
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#define RESTORE_FP(register,offset) lfd register,SAVE_AT(offset)(r1)
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#define SAVE_V(register,offset) \
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li r2,SAVE_AT(offset) XX \
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stvxl register,r2,r1
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#define RESTORE_V(register,offset) \
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li r2,SAVE_AT(offset) XX \
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lvxl register,r2,r1
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#define PROLOGUE \
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mflr r0 XX /* get caller's return address */ \
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stwu r1,-FRAME(r1) XX /* create a stack frame to hold non-volatile registers */ \
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SAVE_LR(r0)
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#define EPILOGUE \
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LOAD_LR(r0) XX \
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lwz r1,0(r1) XX /* destroy the stack frame */ \
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mtlr r0 /* get ready to return */
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/* We have to save and restore nonvolatile registers because
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the Factor compiler treats the entire register file as volatile. */
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DEF(void,c_to_factor,(cell quot, void *vm)):
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PROLOGUE
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SAVE_INT(r13,0)
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SAVE_INT(r14,1)
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SAVE_INT(VM_REG,2)
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SAVE_INT(r16,3)
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SAVE_INT(r17,4)
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SAVE_INT(r18,5)
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SAVE_INT(r19,6)
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SAVE_INT(r20,7)
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SAVE_INT(r21,8)
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SAVE_INT(r22,9)
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SAVE_INT(r23,10)
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SAVE_INT(r24,11)
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SAVE_INT(r25,12)
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SAVE_INT(r26,13)
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SAVE_INT(r27,14)
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SAVE_INT(r28,15)
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SAVE_INT(r29,16)
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SAVE_INT(r30,17)
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SAVE_INT(r31,18)
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SAVE_FP(f14,20)
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SAVE_FP(f15,22)
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SAVE_FP(f16,24)
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SAVE_FP(f17,26)
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SAVE_FP(f18,28)
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SAVE_FP(f19,30)
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SAVE_FP(f20,32)
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SAVE_FP(f21,34)
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SAVE_FP(f22,36)
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SAVE_FP(f23,38)
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SAVE_FP(f24,40)
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SAVE_FP(f25,42)
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SAVE_FP(f26,44)
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SAVE_FP(f27,46)
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SAVE_FP(f28,48)
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SAVE_FP(f29,50)
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SAVE_FP(f30,52)
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SAVE_FP(f31,54)
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SAVE_V(v20,56)
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SAVE_V(v21,60)
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SAVE_V(v22,64)
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SAVE_V(v23,68)
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SAVE_V(v24,72)
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SAVE_V(v25,76)
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SAVE_V(v26,80)
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SAVE_V(v27,84)
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SAVE_V(v28,88)
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SAVE_V(v29,92)
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SAVE_V(v30,96)
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SAVE_V(v31,100)
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/* r4 vm ptr preserved */
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mfvscr v0
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li r2,SAVE_AT(104)
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stvxl v0,r2,r1
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addi r2,r2,0xc
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lwzx r5,r2,r1
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lis r6,0x1
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andc r5,r5,r6
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stwx r5,r2,r1
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subi r2,r2,0xc
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lvxl v0,r2,r1
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mtvscr v0
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/* Load context */
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mr VM_REG,r4
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lwz r16,0(VM_REG)
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/* Load ctx->datastack */
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lwz DS_REG,8(r16)
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/* Load ctx->retainstack */
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lwz RS_REG,12(r16)
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/* Save ctx->callstack_bottom */
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stw r1,4(r16)
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CALL_QUOT
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/* Load context */
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lwz r16,0(VM_REG)
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/* Save ctx->datastack */
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stw DS_REG,8(r16)
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/* Save ctx->retainstack */
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stw RS_REG,12(r16)
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RESTORE_V(v0,104)
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mtvscr v0
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RESTORE_V(v31,100)
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RESTORE_V(v30,96)
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RESTORE_V(v29,92)
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RESTORE_V(v28,88)
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RESTORE_V(v27,84)
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RESTORE_V(v26,80)
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RESTORE_V(v25,76)
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RESTORE_V(v24,72)
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RESTORE_V(v23,68)
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RESTORE_V(v22,64)
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RESTORE_V(v21,60)
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RESTORE_V(v20,56)
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RESTORE_FP(f31,54)
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RESTORE_FP(f30,52)
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RESTORE_FP(f29,50)
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RESTORE_FP(f28,48)
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RESTORE_FP(f27,46)
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RESTORE_FP(f26,44)
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RESTORE_FP(f25,42)
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RESTORE_FP(f24,40)
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RESTORE_FP(f23,38)
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RESTORE_FP(f22,36)
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RESTORE_FP(f21,34)
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RESTORE_FP(f20,32)
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RESTORE_FP(f19,30)
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RESTORE_FP(f18,28)
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RESTORE_FP(f17,26)
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RESTORE_FP(f16,24)
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RESTORE_FP(f15,22)
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RESTORE_FP(f14,20)
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RESTORE_INT(r31,18)
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RESTORE_INT(r30,17)
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RESTORE_INT(r29,16)
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RESTORE_INT(r28,15)
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RESTORE_INT(r27,14)
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RESTORE_INT(r26,13)
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RESTORE_INT(r25,12)
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RESTORE_INT(r24,11)
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RESTORE_INT(r23,10)
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RESTORE_INT(r22,9)
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RESTORE_INT(r21,8)
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RESTORE_INT(r20,7)
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RESTORE_INT(r19,6)
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RESTORE_INT(r18,5)
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RESTORE_INT(r17,4)
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RESTORE_INT(r16,3)
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RESTORE_INT(VM_REG,2)
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RESTORE_INT(r14,1)
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RESTORE_INT(r13,0)
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EPILOGUE
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blr
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DEF(void,set_callstack,(void *vm, stack_frame *to, stack_frame *from, cell length, void *memcpy)):
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/* Save VM pointer in non-volatile register */
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mr VM_REG,r3
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/* Compute new stack pointer */
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sub r1,r4,r6
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/* Call memcpy() */
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mr r3,r1
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mr r4,r5
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mr r5,r6
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stwu r1,-64(r1)
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mtlr r7
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blrl
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lwz r1,0(r1)
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/* Load context */
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lwz r16,0(VM_REG)
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/* Load ctx->datastack */
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lwz DS_REG,8(r16)
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/* Load ctx->retainstack */
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lwz RS_REG,12(r16)
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/* We have changed the stack; load return address again */
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lwz r0,LR_SAVE(r1)
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mtlr r0
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blr
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DEF(void,throw_impl,(cell quot, void *new_stack, void *vm)):
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/* compute new stack pointer */
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mr r1,r4
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/* make vm ptr 2nd arg in case quot->xt == lazy_jit_compile */
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mr r4,r5
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/* Load context */
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mr VM_REG,r5
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lwz r16,0(VM_REG)
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/* Load ctx->datastack */
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lwz DS_REG,8(r16)
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/* Load ctx->retainstack */
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lwz RS_REG,12(r16)
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/* We have changed the stack; load return address again */
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lwz r0,LR_SAVE(r1)
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mtlr r0
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/* Call the quotation */
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JUMP_QUOT
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DEF(void,lazy_jit_compile_impl,(cell quot, void *vm)):
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/* Load context */
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mr VM_REG,r4
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lwz r16,0(VM_REG)
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/* Save ctx->datastack */
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stw DS_REG,8(r16)
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/* Save ctx->retainstack */
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stw RS_REG,12(r16)
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/* Save ctx->callstack_top */
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stw r1,0(r16)
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/* Compile quotation */
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PROLOGUE
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bl MANGLE(lazy_jit_compile)
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EPILOGUE
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/* Call the quotation */
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JUMP_QUOT
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/* Thanks to Joshua Grams for this code.
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On PowerPC processors, we must flush the instruction cache manually
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after writing to the code heap. */
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DEF(void,flush_icache,(void *start, int len)):
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/* compute number of cache lines to flush */
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add r4,r4,r3
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clrrwi r3,r3,5 /* align addr to next lower cache line boundary */
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sub r4,r4,r3 /* then n_lines = (len + 0x1f) / 0x20 */
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addi r4,r4,0x1f
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srwi. r4,r4,5 /* note '.' suffix */
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beqlr /* if n_lines == 0, just return. */
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mtctr r4 /* flush cache lines */
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0: dcbf 0,r3 /* for each line... */
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sync
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icbi 0,r3
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addi r3,r3,0x20
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bdnz 0b
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sync /* finish up */
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isync
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blr
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DEF(void,get_ppc_fpu_env,(void*)):
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mffs f0
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stfd f0,0(r3)
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blr
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DEF(void,set_ppc_fpu_env,(const void*)):
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lfd f0,0(r3)
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mtfsf 0xff,f0
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blr
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DEF(void,get_ppc_vmx_env,(void*)):
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mfvscr v0
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subi r4,r1,16
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li r5,0xf
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andc r4,r4,r5
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stvxl v0,0,r4
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li r5,0xc
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lwzx r6,r5,r4
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stw r6,0(r3)
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blr
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DEF(void,set_ppc_vmx_env,(const void*)):
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subi r4,r1,16
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li r5,0xf
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andc r4,r4,r5
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li r5,0xc
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lwz r6,0(r3)
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stwx r6,r5,r4
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lvxl v0,0,r4
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mtvscr v0
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blr
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