compiler.cfg.linear-scan: cleanups
Slava Pestov
parent
d23bb19b55
commit
43fc230c69
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@ -39,7 +39,7 @@ M: insn compute-stack-frame*
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] when ;
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! PowerPC backend sets frame-required? for ##integer>float!
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\ _spill t frame-required? set-word-prop
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\ ##spill t frame-required? set-word-prop
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\ ##unary-float-function t frame-required? set-word-prop
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\ ##binary-float-function t frame-required? set-word-prop
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@ -706,7 +706,22 @@ temp: temp1/int-rep temp2/int-rep ;
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INSN: ##call-gc
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literal: gc-roots ;
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! Spills and reloads, inserted by register allocator
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TUPLE: spill-slot { n integer } ;
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C: <spill-slot> spill-slot
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INSN: ##spill
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use: src
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literal: rep dst ;
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INSN: ##reload
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def: dst
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literal: rep src ;
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! Instructions used by machine IR only.
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INSN: _spill-area-size
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literal: n ;
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INSN: _prologue
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literal: stack-frame ;
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@ -727,20 +742,6 @@ literal: label ;
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INSN: _conditional-branch
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literal: label insn ;
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TUPLE: spill-slot { n integer } ;
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C: <spill-slot> spill-slot
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INSN: _spill
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use: src
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literal: rep dst ;
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INSN: _reload
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def: dst
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literal: rep src ;
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INSN: _spill-area-size
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literal: n ;
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UNION: ##allocation
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##allot
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##box-alien
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@ -9,11 +9,11 @@ compiler.cfg.linear-scan.allocation.state ;
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IN: compiler.cfg.linear-scan.allocation
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: active-positions ( new assoc -- )
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[ vreg>> active-intervals-for ] dip
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[ active-intervals-for ] dip
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'[ [ 0 ] dip reg>> _ add-use-position ] each ;
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: inactive-positions ( new assoc -- )
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[ [ vreg>> inactive-intervals-for ] keep ] dip
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[ [ inactive-intervals-for ] keep ] dip
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'[
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[ _ relevant-ranges intersect-live-ranges 1/0. or ] [ reg>> ] bi
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_ add-use-position
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@ -17,13 +17,13 @@ ERROR: bad-live-ranges interval ;
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] [ drop ] if ;
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: trim-before-ranges ( live-interval -- )
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[ ranges>> ] [ uses>> last n>> 1 + ] bi
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[ ranges>> ] [ last-use n>> 1 + ] bi
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[ '[ from>> _ <= ] filter! drop ]
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[ swap last (>>to) ]
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2bi ;
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: trim-after-ranges ( live-interval -- )
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[ ranges>> ] [ uses>> first n>> ] bi
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[ ranges>> ] [ first-use n>> ] bi
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[ '[ to>> _ >= ] filter! drop ]
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[ swap first (>>from) ]
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2bi ;
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@ -73,12 +73,12 @@ ERROR: bad-live-ranges interval ;
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'[ [ _ find-use-position ] [ reg>> ] bi _ add-use-position ] each ;
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: active-positions ( new assoc -- )
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[ [ vreg>> active-intervals-for ] keep ] dip
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[ [ active-intervals-for ] keep ] dip
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find-use-positions ;
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: inactive-positions ( new assoc -- )
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[
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[ vreg>> inactive-intervals-for ] keep
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[ inactive-intervals-for ] keep
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[ '[ _ intervals-intersect? ] filter ] keep
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] dip
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find-use-positions ;
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@ -89,7 +89,7 @@ ERROR: bad-live-ranges interval ;
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>alist alist-max ;
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: spill-new? ( new pair -- ? )
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[ uses>> first n>> ] [ second ] bi* > ;
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[ first-use n>> ] [ second ] bi* > ;
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: spill-new ( new pair -- )
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drop spill-after add-unhandled ;
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@ -103,13 +103,13 @@ ERROR: bad-live-ranges interval ;
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! If there is an active interval using 'reg' (there should be at
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! most one) are split and spilled and removed from the inactive
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! set.
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new vreg>> active-intervals-for [ [ reg>> reg = ] find swap dup ] keep
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new active-intervals-for [ [ reg>> reg = ] find swap dup ] keep
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'[ _ remove-nth! drop new start>> spill ] [ 2drop ] if ;
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:: spill-intersecting-inactive ( new reg -- )
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! Any inactive intervals using 'reg' are split and spilled
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! and removed from the inactive set.
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new vreg>> inactive-intervals-for [
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new inactive-intervals-for [
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dup reg>> reg = [
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dup new intervals-intersect? [
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new start>> spill f
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@ -26,14 +26,14 @@ SYMBOL: registers
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! Vector of active live intervals
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SYMBOL: active-intervals
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: active-intervals-for ( vreg -- seq )
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rep-of reg-class-of active-intervals get at ;
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: active-intervals-for ( live-interval -- seq )
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reg-class>> active-intervals get at ;
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: add-active ( live-interval -- )
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dup vreg>> active-intervals-for push ;
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dup active-intervals-for push ;
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: delete-active ( live-interval -- )
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dup vreg>> active-intervals-for remove-eq! drop ;
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dup active-intervals-for remove-eq! drop ;
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: assign-free-register ( new registers -- )
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pop >>reg add-active ;
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@ -41,14 +41,14 @@ SYMBOL: active-intervals
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! Vector of inactive live intervals
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SYMBOL: inactive-intervals
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: inactive-intervals-for ( vreg -- seq )
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rep-of reg-class-of inactive-intervals get at ;
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: inactive-intervals-for ( live-interval -- seq )
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reg-class>> inactive-intervals get at ;
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: add-inactive ( live-interval -- )
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dup vreg>> inactive-intervals-for push ;
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dup inactive-intervals-for push ;
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: delete-inactive ( live-interval -- )
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dup vreg>> inactive-intervals-for remove-eq! drop ;
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dup inactive-intervals-for remove-eq! drop ;
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! Vector of handled live intervals
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SYMBOL: handled-intervals
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@ -67,7 +67,7 @@ ERROR: register-already-used live-interval ;
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: check-activate ( live-interval -- )
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check-allocation? get [
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dup [ reg>> ] [ vreg>> active-intervals-for [ reg>> ] map ] bi member?
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dup [ reg>> ] [ active-intervals-for [ reg>> ] map ] bi member?
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[ register-already-used ] [ drop ] if
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] [ drop ] if ;
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@ -148,7 +148,7 @@ SYMBOL: spill-slots
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! A utility used by register-status and spill-status words
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: free-positions ( new -- assoc )
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vreg>> rep-of reg-class-of registers get at
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reg-class>> registers get at
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[ 1/0. ] H{ } <linked-assoc> map>assoc ;
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: add-use-position ( n reg assoc -- ) [ [ min ] when* ] change-at ;
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@ -68,8 +68,10 @@ SYMBOL: register-live-outs
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H{ } clone register-live-outs set
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init-unhandled ;
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: spill-rep ( live-interval -- rep ) vreg>> rep-of ;
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: insert-spill ( live-interval -- )
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[ reg>> ] [ vreg>> rep-of ] [ spill-to>> ] tri _spill ;
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[ reg>> ] [ spill-rep ] [ spill-to>> ] tri ##spill ;
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: handle-spill ( live-interval -- )
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dup spill-to>> [ insert-spill ] [ drop ] if ;
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@ -88,15 +90,17 @@ SYMBOL: register-live-outs
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: expire-old-intervals ( n -- )
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pending-interval-heap get (expire-old-intervals) ;
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: reload-rep ( live-interval -- rep ) vreg>> rep-of ;
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: insert-reload ( live-interval -- )
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[ reg>> ] [ vreg>> rep-of ] [ reload-from>> ] tri _reload ;
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[ reg>> ] [ reload-rep ] [ reload-from>> ] tri ##reload ;
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: insert-reload? ( live-interval -- ? )
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! Don't insert a reload if the register will be written to
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! before being read again.
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{
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[ reload-from>> ]
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[ uses>> first type>> +use+ eq? ]
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[ first-use type>> +use+ eq? ]
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} 1&& ;
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: handle-reload ( live-interval -- )
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@ -89,6 +89,7 @@ H{
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[
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 2 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 1 } } }
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@ -97,6 +98,7 @@ H{
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}
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 } } }
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@ -106,6 +108,7 @@ H{
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] [
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T{ live-interval
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{ vreg 1 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 1 } T{ vreg-use f 5 } } }
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@ -116,6 +119,7 @@ H{
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[
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T{ live-interval
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{ vreg 2 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 1 }
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{ uses V{ T{ vreg-use f 0 } } }
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@ -124,6 +128,7 @@ H{
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class float-regs }
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{ start 1 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 1 } T{ vreg-use f 5 } } }
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@ -133,6 +138,7 @@ H{
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] [
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T{ live-interval
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{ vreg 2 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 1 } T{ vreg-use f 5 } } }
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@ -143,6 +149,7 @@ H{
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[
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 1 }
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{ uses V{ T{ vreg-use f 0 } } }
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@ -151,6 +158,7 @@ H{
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 20 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 20 } T{ vreg-use f 30 } } }
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@ -160,6 +168,7 @@ H{
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] [
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T{ live-interval
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{ vreg 3 }
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{ reg-class float-regs }
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{ start 0 }
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{ end 30 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 20 } T{ vreg-use f 30 } } }
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@ -184,6 +193,7 @@ H{
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V{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ reg 1 }
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{ start 1 }
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{ end 15 }
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@ -191,6 +201,7 @@ H{
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ reg 2 }
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{ start 3 }
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{ end 8 }
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@ -198,6 +209,7 @@ H{
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ reg 3 }
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{ start 3 }
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{ end 10 }
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@ -209,6 +221,7 @@ H{
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H{ } inactive-intervals set
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 } } }
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@ -227,6 +240,7 @@ H{
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V{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ reg 1 }
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{ start 1 }
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{ end 15 }
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@ -234,6 +248,7 @@ H{
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ reg 2 }
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{ start 3 }
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{ end 8 }
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@ -245,6 +260,7 @@ H{
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H{ } inactive-intervals set
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ start 5 }
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{ end 5 }
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{ uses V{ T{ vreg-use f 5 } } }
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@ -258,6 +274,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 100 } } }
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@ -272,6 +289,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 10 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 10 } } }
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@ -279,6 +297,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 11 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 11 } T{ vreg-use f 20 } } }
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@ -293,6 +312,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 100 } } }
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@ -300,6 +320,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 60 }
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{ uses V{ T{ vreg-use f 30 } T{ vreg-use f 60 } } }
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@ -314,6 +335,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 100 } } }
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@ -321,6 +343,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 200 }
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{ uses V{ T{ vreg-use f 30 } T{ vreg-use f 200 } } }
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@ -335,6 +358,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 100 } } }
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@ -342,6 +366,7 @@ H{ { 1 int-rep } { 2 int-rep } } representations set
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 30 }
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{ end 100 }
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{ uses V{ T{ vreg-use f 30 } T{ vreg-use f 100 } } }
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@ -365,6 +390,7 @@ H{
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{
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T{ live-interval
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{ vreg 1 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 10 } T{ vreg-use f 20 } } }
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@ -372,6 +398,7 @@ H{
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}
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T{ live-interval
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{ vreg 2 }
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{ reg-class int-regs }
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{ start 0 }
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{ end 20 }
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{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 10 } T{ vreg-use f 20 } } }
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@ -379,6 +406,7 @@ H{
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}
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T{ live-interval
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{ vreg 3 }
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 6 } } }
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@ -386,6 +414,7 @@ H{
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}
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T{ live-interval
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{ vreg 4 }
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
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{ uses V{ T{ vreg-use f 8 } } }
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|
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@ -395,6 +424,7 @@ H{
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! This guy will invoke the 'spill partially available' code path
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T{ live-interval
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{ vreg 5 }
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{ reg-class int-regs }
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{ start 4 }
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{ end 8 }
|
||||
{ uses V{ T{ vreg-use f 8 } } }
|
||||
|
|
@ -411,6 +441,7 @@ H{
|
|||
{
|
||||
T{ live-interval
|
||||
{ vreg 1 }
|
||||
{ reg-class int-regs }
|
||||
{ start 0 }
|
||||
{ end 10 }
|
||||
{ uses V{ T{ vreg-use f 0 } T{ vreg-use f 6 } T{ vreg-use f 10 } } }
|
||||
|
|
@ -420,6 +451,7 @@ H{
|
|||
! This guy will invoke the 'spill new' code path
|
||||
T{ live-interval
|
||||
{ vreg 5 }
|
||||
{ reg-class int-regs }
|
||||
{ start 2 }
|
||||
{ end 8 }
|
||||
{ uses V{ T{ vreg-use f 8 } } }
|
||||
|
|
@ -491,12 +523,14 @@ H{
|
|||
[ 5 ] [
|
||||
T{ live-interval
|
||||
{ start 0 }
|
||||
{ reg-class int-regs }
|
||||
{ end 10 }
|
||||
{ uses { 0 10 } }
|
||||
{ ranges V{ T{ live-range f 0 10 } } }
|
||||
}
|
||||
T{ live-interval
|
||||
{ start 5 }
|
||||
{ reg-class int-regs }
|
||||
{ end 10 }
|
||||
{ uses { 5 10 } }
|
||||
{ ranges V{ T{ live-range f 5 10 } } }
|
||||
|
|
@ -520,6 +554,7 @@ H{
|
|||
{
|
||||
T{ live-interval
|
||||
{ vreg 1 }
|
||||
{ reg-class int-regs }
|
||||
{ start 0 }
|
||||
{ end 20 }
|
||||
{ reg 0 }
|
||||
|
|
@ -529,6 +564,7 @@ H{
|
|||
|
||||
T{ live-interval
|
||||
{ vreg 2 }
|
||||
{ reg-class int-regs }
|
||||
{ start 4 }
|
||||
{ end 40 }
|
||||
{ reg 0 }
|
||||
|
|
@ -543,6 +579,7 @@ H{
|
|||
{
|
||||
T{ live-interval
|
||||
{ vreg 3 }
|
||||
{ reg-class int-regs }
|
||||
{ start 0 }
|
||||
{ end 40 }
|
||||
{ reg 1 }
|
||||
|
|
@ -554,7 +591,8 @@ H{
|
|||
} active-intervals set
|
||||
|
||||
T{ live-interval
|
||||
{ vreg 4 }
|
||||
{ vreg 4 }
|
||||
{ reg-class int-regs }
|
||||
{ start 8 }
|
||||
{ end 10 }
|
||||
{ ranges V{ T{ live-range f 8 10 } } }
|
||||
|
|
@ -924,13 +962,13 @@ test-diamond
|
|||
|
||||
[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
|
||||
|
||||
[ _spill ] [ 2 get successors>> first instructions>> first class ] unit-test
|
||||
[ ##spill ] [ 2 get successors>> first instructions>> first class ] unit-test
|
||||
|
||||
[ _spill ] [ 3 get instructions>> second class ] unit-test
|
||||
[ ##spill ] [ 3 get instructions>> second class ] unit-test
|
||||
|
||||
[ f ] [ 3 get instructions>> [ _reload? ] any? ] unit-test
|
||||
[ f ] [ 3 get instructions>> [ ##reload? ] any? ] unit-test
|
||||
|
||||
[ _reload ] [ 4 get instructions>> first class ] unit-test
|
||||
[ ##reload ] [ 4 get instructions>> first class ] unit-test
|
||||
|
||||
! Resolve pass
|
||||
V{
|
||||
|
|
@ -978,11 +1016,11 @@ V{
|
|||
|
||||
[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
|
||||
|
||||
[ t ] [ 2 get instructions>> [ _spill? ] any? ] unit-test
|
||||
[ t ] [ 2 get instructions>> [ ##spill? ] any? ] unit-test
|
||||
|
||||
[ t ] [ 3 get predecessors>> first instructions>> [ _spill? ] any? ] unit-test
|
||||
[ t ] [ 3 get predecessors>> first instructions>> [ ##spill? ] any? ] unit-test
|
||||
|
||||
[ t ] [ 5 get instructions>> [ _reload? ] any? ] unit-test
|
||||
[ t ] [ 5 get instructions>> [ ##reload? ] any? ] unit-test
|
||||
|
||||
! A more complicated failure case with resolve that came up after the above
|
||||
! got fixed
|
||||
|
|
@ -1041,13 +1079,13 @@ V{
|
|||
|
||||
[ ] [ { 1 2 3 4 } test-linear-scan-on-cfg ] unit-test
|
||||
|
||||
[ _spill ] [ 1 get instructions>> second class ] unit-test
|
||||
[ _reload ] [ 4 get instructions>> 4 swap nth class ] unit-test
|
||||
[ V{ 3 2 1 } ] [ 8 get instructions>> [ _spill? ] filter [ dst>> n>> cell / ] map ] unit-test
|
||||
[ V{ 3 2 1 } ] [ 9 get instructions>> [ _reload? ] filter [ src>> n>> cell / ] map ] unit-test
|
||||
[ ##spill ] [ 1 get instructions>> second class ] unit-test
|
||||
[ ##reload ] [ 4 get instructions>> 4 swap nth class ] unit-test
|
||||
[ V{ 3 2 1 } ] [ 8 get instructions>> [ ##spill? ] filter [ dst>> n>> cell / ] map ] unit-test
|
||||
[ V{ 3 2 1 } ] [ 9 get instructions>> [ ##reload? ] filter [ src>> n>> cell / ] map ] unit-test
|
||||
|
||||
! Resolve pass should insert this
|
||||
[ _reload ] [ 5 get predecessors>> first instructions>> first class ] unit-test
|
||||
[ ##reload ] [ 5 get predecessors>> first instructions>> first class ] unit-test
|
||||
|
||||
! Some random bug
|
||||
V{
|
||||
|
|
@ -1397,13 +1435,13 @@ test-diamond
|
|||
|
||||
[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
|
||||
|
||||
[ 0 ] [ 1 get instructions>> [ _spill? ] count ] unit-test
|
||||
[ 0 ] [ 1 get instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 1 ] [ 2 get instructions>> [ _spill? ] count ] unit-test
|
||||
[ 1 ] [ 2 get instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 1 ] [ 3 get predecessors>> first instructions>> [ _spill? ] count ] unit-test
|
||||
[ 1 ] [ 3 get predecessors>> first instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 1 ] [ 4 get instructions>> [ _reload? ] count ] unit-test
|
||||
[ 1 ] [ 4 get instructions>> [ ##reload? ] count ] unit-test
|
||||
|
||||
! Another test case for fencepost error in assignment pass
|
||||
V{ T{ ##branch } } 0 test-bb
|
||||
|
|
@ -1435,12 +1473,12 @@ test-diamond
|
|||
|
||||
[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
|
||||
|
||||
[ 0 ] [ 1 get instructions>> [ _spill? ] count ] unit-test
|
||||
[ 0 ] [ 1 get instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 1 ] [ 2 get instructions>> [ _spill? ] count ] unit-test
|
||||
[ 1 ] [ 2 get instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 1 ] [ 2 get instructions>> [ _reload? ] count ] unit-test
|
||||
[ 1 ] [ 2 get instructions>> [ ##reload? ] count ] unit-test
|
||||
|
||||
[ 0 ] [ 3 get instructions>> [ _spill? ] count ] unit-test
|
||||
[ 0 ] [ 3 get instructions>> [ ##spill? ] count ] unit-test
|
||||
|
||||
[ 0 ] [ 4 get instructions>> [ _reload? ] count ] unit-test
|
||||
[ 0 ] [ 4 get instructions>> [ ##reload? ] count ] unit-test
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
USING: namespaces kernel assocs accessors sequences math math.order fry
|
||||
combinators binary-search compiler.cfg.instructions compiler.cfg.registers
|
||||
compiler.cfg.def-use compiler.cfg.liveness compiler.cfg.linearization.order
|
||||
compiler.cfg ;
|
||||
compiler.cfg cpu.architecture ;
|
||||
IN: compiler.cfg.linear-scan.live-intervals
|
||||
|
||||
TUPLE: live-range from to ;
|
||||
|
|
@ -19,7 +19,12 @@ C: <vreg-use> vreg-use
|
|||
TUPLE: live-interval
|
||||
vreg
|
||||
reg spill-to reload-from
|
||||
start end ranges uses ;
|
||||
start end ranges uses
|
||||
reg-class ;
|
||||
|
||||
: first-use ( live-interval -- use ) uses>> first ; inline
|
||||
|
||||
: last-use ( live-interval -- use ) uses>> last ; inline
|
||||
|
||||
GENERIC: covers? ( insn# obj -- ? )
|
||||
|
||||
|
|
@ -66,6 +71,7 @@ M: live-interval covers? ( insn# live-interval -- ? )
|
|||
\ live-interval new
|
||||
V{ } clone >>uses
|
||||
V{ } clone >>ranges
|
||||
over rep-of reg-class-of >>reg-class
|
||||
swap >>vreg ;
|
||||
|
||||
: block-from ( bb -- n ) instructions>> first insn#>> 1 - ;
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ IN: compiler.cfg.linear-scan.resolve.tests
|
|||
|
||||
[
|
||||
{
|
||||
T{ _reload { dst 1 } { rep int-rep } { src T{ spill-slot f 0 } } }
|
||||
T{ ##reload { dst 1 } { rep int-rep } { src T{ spill-slot f 0 } } }
|
||||
}
|
||||
] [
|
||||
[
|
||||
|
|
@ -32,7 +32,7 @@ IN: compiler.cfg.linear-scan.resolve.tests
|
|||
|
||||
[
|
||||
{
|
||||
T{ _spill { src 1 } { rep int-rep } { dst T{ spill-slot f 0 } } }
|
||||
T{ ##spill { src 1 } { rep int-rep } { dst T{ spill-slot f 0 } } }
|
||||
}
|
||||
] [
|
||||
[
|
||||
|
|
@ -66,8 +66,8 @@ IN: compiler.cfg.linear-scan.resolve.tests
|
|||
|
||||
[
|
||||
{
|
||||
T{ _spill { src 0 } { rep int-rep } { dst T{ spill-slot f 0 } } }
|
||||
T{ _reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 1 } } }
|
||||
T{ ##spill { src 0 } { rep int-rep } { dst T{ spill-slot f 0 } } }
|
||||
T{ ##reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 1 } } }
|
||||
T{ ##branch }
|
||||
}
|
||||
] [
|
||||
|
|
@ -80,8 +80,8 @@ IN: compiler.cfg.linear-scan.resolve.tests
|
|||
|
||||
[
|
||||
{
|
||||
T{ _spill { src 0 } { rep int-rep } { dst T{ spill-slot f 1 } } }
|
||||
T{ _reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 0 } } }
|
||||
T{ ##spill { src 0 } { rep int-rep } { dst T{ spill-slot f 1 } } }
|
||||
T{ ##reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 0 } } }
|
||||
T{ ##branch }
|
||||
}
|
||||
] [
|
||||
|
|
@ -94,8 +94,8 @@ IN: compiler.cfg.linear-scan.resolve.tests
|
|||
|
||||
[
|
||||
{
|
||||
T{ _spill { src 0 } { rep int-rep } { dst T{ spill-slot f 1 } } }
|
||||
T{ _reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 0 } } }
|
||||
T{ ##spill { src 0 } { rep int-rep } { dst T{ spill-slot f 1 } } }
|
||||
T{ ##reload { dst 0 } { rep tagged-rep } { src T{ spill-slot f 0 } } }
|
||||
T{ ##branch }
|
||||
}
|
||||
] [
|
||||
|
|
@ -116,15 +116,15 @@ H{ } clone spill-temps set
|
|||
}
|
||||
mapping-instructions {
|
||||
{
|
||||
T{ _spill { src 0 } { rep int-rep } { dst T{ spill-slot f 8 } } }
|
||||
T{ ##spill { src 0 } { rep int-rep } { dst T{ spill-slot f 8 } } }
|
||||
T{ ##copy { dst 0 } { src 1 } { rep int-rep } }
|
||||
T{ _reload { dst 1 } { rep int-rep } { src T{ spill-slot f 8 } } }
|
||||
T{ ##reload { dst 1 } { rep int-rep } { src T{ spill-slot f 8 } } }
|
||||
T{ ##branch }
|
||||
}
|
||||
{
|
||||
T{ _spill { src 1 } { rep int-rep } { dst T{ spill-slot f 8 } } }
|
||||
T{ ##spill { src 1 } { rep int-rep } { dst T{ spill-slot f 8 } } }
|
||||
T{ ##copy { dst 1 } { src 0 } { rep int-rep } }
|
||||
T{ _reload { dst 0 } { rep int-rep } { src T{ spill-slot f 8 } } }
|
||||
T{ ##reload { dst 0 } { rep int-rep } { src T{ spill-slot f 8 } } }
|
||||
T{ ##branch }
|
||||
}
|
||||
} member?
|
||||
|
|
|
|||
|
|
@ -51,16 +51,16 @@ SYMBOL: spill-temps
|
|||
] if ;
|
||||
|
||||
: memory->register ( from to -- )
|
||||
swap [ reg>> ] [ [ rep>> ] [ reg>> ] bi ] bi* _reload ;
|
||||
swap [ reg>> ] [ [ rep>> ] [ reg>> ] bi ] bi* ##reload ;
|
||||
|
||||
: register->memory ( from to -- )
|
||||
[ [ reg>> ] [ rep>> ] bi ] [ reg>> ] bi* _spill ;
|
||||
[ [ reg>> ] [ rep>> ] bi ] [ reg>> ] bi* ##spill ;
|
||||
|
||||
: temp->register ( from to -- )
|
||||
nip [ reg>> ] [ rep>> ] [ rep>> spill-temp ] tri _reload ;
|
||||
nip [ reg>> ] [ rep>> ] [ rep>> spill-temp ] tri ##reload ;
|
||||
|
||||
: register->temp ( from to -- )
|
||||
drop [ [ reg>> ] [ rep>> ] bi ] [ rep>> spill-temp ] bi _spill ;
|
||||
drop [ [ reg>> ] [ rep>> ] bi ] [ rep>> spill-temp ] bi ##spill ;
|
||||
|
||||
: register->register ( from to -- )
|
||||
swap [ reg>> ] [ [ reg>> ] [ rep>> ] bi ] bi* ##copy ;
|
||||
|
|
|
|||
|
|
@ -200,7 +200,8 @@ CODEGEN: ##vm-field %vm-field
|
|||
CODEGEN: ##set-vm-field %set-vm-field
|
||||
CODEGEN: ##alien-global %alien-global
|
||||
CODEGEN: ##call-gc %call-gc
|
||||
|
||||
CODEGEN: ##spill %spill
|
||||
CODEGEN: ##reload %reload
|
||||
CODEGEN: ##dispatch %dispatch
|
||||
|
||||
: %dispatch-label ( label -- )
|
||||
|
|
@ -210,8 +211,6 @@ CODEGEN: ##dispatch %dispatch
|
|||
CODEGEN: _label resolve-label
|
||||
CODEGEN: _dispatch-label %dispatch-label
|
||||
CODEGEN: _branch %jump-label
|
||||
CODEGEN: _spill %spill
|
||||
CODEGEN: _reload %reload
|
||||
CODEGEN: _loop-entry %loop-entry
|
||||
|
||||
GENERIC: generate-conditional-insn ( label insn -- )
|
||||
|
|
|
|||
Loading…
Reference in New Issue