compiler.cfg.linear-scan.*: stub docs and tests

basis/compiler/cfg/linear-scan/allocation/state/state.factor

@@ -130,7 +130,6 @@ SYMBOL: unhandled-intervals
 ! Minheap of sync points which still need to be processed
 SYMBOL: unhandled-sync-points
 
-! Mapping from vregs to spill slots
 SYMBOL: spill-slots
 
 : assign-spill-slot ( coalesced-vreg rep -- spill-slot )

basis/compiler/cfg/linear-scan/assignment/assignment-docs.factor

@@ -7,8 +7,13 @@ HELP: assign-registers-in-insn
 
 HELP: assign-gc-roots
 { $values { "gc-map" gc-map } }
-{ $description "Assigns spill slots for all gc roots in a gc map." }
+{ $description "Assigns spill slots for all gc roots in a gc map." } ;
-{ $see-also spill-slot } ;
+
+HELP: assign-derived-roots
+{ $values { "gc-map" gc-map } }
+{ $description "Assigns pairs of spill slots for all derived roots in a gc map." } ;
+
+{ assign-gc-roots assign-derived-roots } related-words
 
 HELP: vreg>reg
 { $values { "vreg" "virtaul register" } { "reg" "register" } }

basis/compiler/cfg/linear-scan/assignment/assignment-tests.factor

@@ -0,0 +1,10 @@
+USING: compiler.cfg.instructions compiler.cfg.linear-scan.assignment
+compiler.cfg.linear-scan.live-intervals cpu.x86.assembler.operands make
+tools.test ;
+IN: compiler.cfg.linear-scan.assignment.tests
+
+{ { T{ ##spill { src RAX } } } } [
+    [
+        T{ live-interval-state { vreg 1234 } { reg RAX } } insert-spill
+    ] { } make
+] unit-test

basis/compiler/cfg/linear-scan/assignment/assignment.factor

@@ -31,8 +31,6 @@ SYMBOL: pending-interval-assoc
     vreg>> pending-interval-assoc get delete-at ;
 
 :: vreg>reg ( vreg -- reg )
-    ! If a live vreg is not in the pending set, then it must
-    ! have been spilled.
     vreg leader :> leader
     leader pending-interval-assoc get at* [
         drop leader vreg rep-of lookup-spill-slot