cpu.x86.64: inline cache miss blocks have a prolog generated in the middle of a procedure; undo a recent change to non-optimizing backend to fix random crashes

2010-02-06 18:41:58 +13:00 · 2010-02-06 18:41:58 +13:00 · d5a25f99bf
parent daefa86b6d
commit d5a25f99bf
1 changed files with 1 additions and 1 deletions
--- a/basis/cpu/x86/64/bootstrap.factor
+++ b/basis/cpu/x86/64/bootstrap.factor
@ -28,7 +28,7 @@ IN: bootstrap.x86

 [
    ! load entry point
-    safe-reg -7 [] LEA
+    safe-reg 0 MOV rc-absolute-cell rt-this jit-rel
    ! save stack frame size
    stack-frame-size PUSH
    ! push entry point