Slava Pestov
b2ea3afd84
math.vectors.simd: add hlshift, hrshift (128-bit shift), vbitandn intrinsics
2009-09-28 02:17:46 -05:00
Slava Pestov
59fbe85c9b
compiler.cfg: nuke ##bignum>integer and ##integer>bignum since they were unused
2009-09-27 20:36:05 -05:00
Slava Pestov
f757b454cc
Merge branch 'master' into more_aggressive_coalescing
2009-09-27 19:29:50 -05:00
Slava Pestov
705b4ab5c3
compiler.cfg.linear-scan: fix partial sync point logic in case where dst == src, and clean up spilling code
2009-09-27 19:28:20 -05:00
Slava Pestov
1e841e5086
compiler.cfg.ssa.destruction: more aggressive coalescing work in progress
2009-09-27 17:17:26 -05:00
sheeple
01a4047126
Merge branch 'slots' of git://factorcode.org/git/factor into slots
...
Conflicts:
basis/cpu/x86/x86.factor
2009-09-26 03:12:42 -05:00
Daniel Ehrenberg
51f2bbd74b
Completing slot and set-slot changes on x86
2009-09-26 01:39:48 -05:00
Phil Dawes
d457df1fbf
moved %(un)nest-stacks out to cpu specific files to eliminate %vm-invoke from compiler.codegen
2009-09-25 19:32:08 +01:00
Phil Dawes
28420c587a
isolated %vm-invoke-blah-arg crap to 64.factor
2009-09-25 19:02:41 +01:00
Phil Dawes
a07a2f7496
compiler.codegen passes temp reg to %call-gc
2009-09-25 18:48:13 +01:00
Slava Pestov
7b6128dd03
math.vectors.simd: add v<< and v>> intrinsics for bitwise shifts on elements
2009-09-24 03:32:39 -05:00
Slava Pestov
dfc9fd071e
Add longlong-2, ulonglong-2, longlong-4, ulonglong-4 SIMD types, fix int-4 multiplication on SSE2
2009-09-23 20:23:25 -05:00
Slava Pestov
43fa252af5
math.vectors.simd: new operations: vabs vsqrt vbitand vbitor vbitxor
2009-09-23 02:47:14 -05:00
Slava Pestov
9d90bdd439
Fix conflict
2009-09-20 23:18:07 -05:00
Slava Pestov
ea44ea3522
math.vectors.simd: add saturated arithmetic operations
2009-09-20 23:16:02 -05:00
Slava Pestov
acea55c692
math.vectors: add v+- word which is accelerated by SSE3
2009-09-20 17:43:16 -05:00
Slava Pestov
e77341b90c
math.vectors.simd: redesign to be more flexible, integer SIMD work in progress
2009-09-20 02:08:32 -05:00
Phil Dawes
0bc7c0c1d0
separated vm-1st-arg and vm-3rd-arg asm invoke words (needed for ppc & x86.64)
2009-09-16 08:20:09 +01:00
Phil Dawes
ff54a57eb3
added code to pass vm ptr to some unboxers
2009-09-16 08:16:32 +01:00
Phil Dawes
ff8f2b10ec
fixed up getenv compiler intrinsic to use vm struct userenv
2009-09-16 08:16:32 +01:00
Phil Dawes
6a193bb0d5
Added %vm-invoke to pass vm ptr to vm functions (x86.32 only, otherwise uses singleton vm)
2009-09-16 08:16:30 +01:00
Slava Pestov
7e2f0e5dbf
compiler: separate ##save-context instruction from ##alien-invoke, generate a ##save-context for libm calls, and add a pass to combine multiple context saves within a basic block. Fixes crashes with FP traps thrown by libm functions on x86-32
2009-09-08 21:50:55 -05:00
Joe Groff
0ea9949e51
split unordered and ordered float comparison intrinsics in compiler; generate only unordered comparisons for now
2009-09-08 17:04:26 -05:00
Slava Pestov
1e5bc3b376
inline alien-vector and set-alien-vector if SIMD is not available for a small speedup
2009-09-08 13:56:17 -05:00
Slava Pestov
e36a0d7ef4
compiler: clean up code generation for alien boxing/unboxing a bit
2009-09-03 21:22:43 -05:00
Slava Pestov
4d5a4222b6
More SIMD work
...
- Rename SIMD types and register representations: <type>-<count> rather than <count><type>-array
- Make a functor to define 256-bit vector types, use it to define float-8 type
- Make SIMD instructions pure-insns so that they participate in value numbering
2009-09-03 20:58:56 -05:00
Slava Pestov
ff8c70dbe0
Initial implementation of SSE vector intrinsics:
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- cpu.architecture: add SSE vector representations
- compiler.cfg.intrinsics.alien: remove an attempt at optimization that value numbering handles now
- compiler.cfg.representations: support instructions where the representation is set in the 'rep' slot, and support conversions between single and double floats
- alien-float, set-alien-float now use the single float representation, and the conversion is implicit; this fixes a long-standing bug where a register could get clobbered because of how %set-alien-float was defined on x86
- math.vectors.specialization: add support for SIMD specialization (where the vector word's body is replaced by another quotation), also specialize the 'sum' word
- math.vectors.simd: 4float-array, 2double-array, 4double-array types, and specializers for the math.vectors words
2009-09-03 02:33:07 -05:00
Slava Pestov
85a2bfab6c
compiler: eliminate boilerplate by centralizing info in declarative INSN: syntax
2009-09-02 06:22:37 -05:00
Slava Pestov
9595be4bf9
%box-displaced-alien: fix clobberage found by Doug
2009-08-30 05:11:08 -05:00
Slava Pestov
0db01f6d5f
compiler.cfg.linear-scan now supports partial sync-points where all registers are spilled; taking advantage of this, there are new trigonometric intrinsics which yield a 2x performance boost on benchmark.struct-arrays and a 25% boost on benchmark.partial-sums
2009-08-30 04:52:01 -05:00
Slava Pestov
2bb6293217
compiler: add fixnum-min/max intrinsics; ~10% speedup on benchmark.yuv-to-rgb
2009-08-28 19:02:59 -05:00
Slava Pestov
d957ae4e44
Performance improvements to make struct-arrays benchmark faster
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- improved optimization of ##unbox-any-c-ptr on ##box-displaced-alien; convert it to ##unbox-c-ptr where possible using class info stored in the ##bda instruction
- make fcos, fsin, etc inline again; everything in math.libm inline again, except for fsqrt which is an intrinsic
- convert min and max on floats to float-min and float-max
- make min and max not inline, so that the above can work
- struct-arrays: rice a bit so that more fixnums come up
2009-08-28 05:21:16 -05:00
Slava Pestov
f662e6403a
compiler: new inline intrinsic for <displaced-alien> where the inputs have known types; value numbering now eliminates unnecessary allocation of displaced aliens if the result is immediately unboxed again
2009-08-27 00:06:19 -05:00
Slava Pestov
0df8aadce2
cpu.x86: use SQRTSD instruction for math.libm:fsqrt word
2009-08-25 23:22:15 -05:00
Slava Pestov
4b7ba38aab
compiler.cfg: virtual registers are integers now, and representations are stored off to the side. Fix bug in representation selection that would manifest if a value was used as a float and a fixnum in different branches; cannot globally unbox float in this case
2009-08-08 04:02:18 -05:00
Slava Pestov
725280d424
Split off the notion of a register representation from a register class
2009-08-07 17:44:50 -05:00
Slava Pestov
45770c6250
Move a bunch of GC check generation logic to platform-independent side
2009-07-30 21:28:27 -05:00
Slava Pestov
be363d1a5b
compiler.cfg: Get inline GC checks working again, using a dataflow analysis to compute uninitialized stack locations in compiler.cfg.stacks.uninitialized. Re-enable intrinsics which use inline allocation
2009-07-30 09:19:44 -05:00
Slava Pestov
3fb4fc1bde
Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases
2009-07-16 23:50:48 -05:00
Slava Pestov
e76dce8aff
Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint
2009-07-16 18:29:40 -05:00
Slava Pestov
9ad9600764
Remove %dispatch-label since its tehe same on all platforms; fix %gc on PowerPC
2009-06-07 21:46:28 -05:00
Slava Pestov
2d231f066a
GC checks now save and restore registers
2009-06-02 18:23:47 -05:00
Slava Pestov
b389dcf441
Redo compiler.codegen.fixup and get %dispatch to work
2009-06-01 02:32:36 -05:00
Slava Pestov
fc152ef210
Various improvements aimed at getting local optimization regressions fixed:
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- Rename _gc to ##gc
- Absolute labels are now supported
- Generate _dispatch-label
2009-05-31 23:28:08 -05:00
Slava Pestov
76d74c16af
Fixing various bugs; alias analysis wasn't handling ##phi nodes, stack analysis incorrectly handled height-changing back edges and ##fixnum-*, clean up ##dispatch generation
2009-05-29 01:39:14 -05:00
Slava Pestov
c93d876075
Better separation of concerns: cpu.{x86,ppc}.assembler no longer depends on compiler.codegen.fixup and cpu.architecture. Rename rt-xt-direct to rt-xt-pic to better explain its purpose
2009-05-06 16:14:53 -05:00
sheeple
facd455e92
Working on complex float support in FFI on NetBSD
2009-02-12 06:25:07 -06:00
Slava Pestov
44bfff7c7b
Rename ##load-indirect to ##load-reference since this is more descriptive; value numbering doesn't assign expressions to ##load-reference nodes since this would end up folding literals which were eq? but not =
2009-01-29 01:44:58 -06:00
Slava Pestov
8a8f0c925c
Use BSR instruction to implement fixnum-log2 intrinsic
2008-12-06 15:31:17 -06:00
Slava Pestov
a56d480aa6
Various optimizations leading to a 10% speedup on compiling empty EBNF parser:
...
- open-code getenv primitive
- inline tuple predicates in finalization
- faster partial dispatch
- faster built-in type predicates
- faster tuple predicates
- faster lo-tag dispatch
- compile V{ } clone and H{ } clone more efficiently
- add fixnum fast-path to =; avoid indirect branch if two fixnums not eq
- faster >alist on hashtables
2008-12-06 09:16:29 -06:00