c00af97fa1
compiler.cfg.linear-scan.resolve: More fixes
2009-07-04 00:45:06 -05:00
da13681bc8
compiler.cfg.linear-scan: redo resolve pass to fix a correctness issue
2009-07-03 23:38:52 -05:00
8d3a45dee2
compiler.cfg: clean up GC check generation to use spill-slot data type
2009-07-03 23:11:23 -05:00
af875ba836
compiler.cfg: bug fixes in GC check insertion and fixnum intrinsics
2009-07-02 00:51:06 -05:00
a19f22ec82
compiler.cfg.linear-scan: debugging spilling and resolve pass
2009-07-01 17:41:07 -05:00
612e4b99b0
compiler.cfg.linear-scan.assignment: insert-copy did the wrong thing if the second interval had been split. Fixes compilation of 'trilerp'
2009-06-30 21:07:39 -05:00
54876d0cba
compiler.cfg.linear-scan.assignment: get check-assignment? to work with coalescing
2009-06-30 18:10:53 -05:00
578b0126fc
compiler.cfg.linear-scan: compute-free-pos was broken in the case where more than one inactive interval had the same physical register assigned
2009-06-30 16:07:58 -05:00
5a78956956
compiler.cfg.linear-scan: Working on resolve pass
2009-06-21 00:20:01 -05:00
c1839200dd
compiler.cfg.linear-scan.assignment: correctly compute live registers at GC check points
2009-06-20 15:33:12 -05:00
64f93e41a9
Various linear scan fixes
...
insert spill before reload to fix x86-32 regression
inactive splitting: if all inactive intervals' registers are in use, don't fail
fix stack analysis tests
2009-06-13 17:35:40 -05:00
d0f6a7d048
Split up compiler.cfg.linear-scan.allocation into a number of sub-vocabularies; start work on compiler.cfg.linear-scan.resolve; start work on inactive interval splitting
2009-06-11 17:55:14 -05:00
04c72d0a72
Linear scan: correctly compute live spill slots
2009-06-05 18:06:47 -05:00
81b2a39070
compiler.cfg.linear-scan: re-do interval splitting to operate on live ranges; add inactive set processing
2009-06-04 18:53:02 -05:00
2d231f066a
GC checks now save and restore registers
2009-06-02 18:23:47 -05:00
32f17f3e14
Fix scoping issue in compiler.cfg.linear-scan.assignment
2009-05-31 18:21:23 -05:00
e04df76f60
Various codegen improvements:
...
- new-insn word to construct instructions
- cache RPO in the CFG
- re-organize low-level optimizer so that MR is built after register allocation
- register allocation now stores instruction numbers in the instructions themselves
- split defs-vregs into defs-vregs and temp-vregs
2009-05-29 13:11:34 -05:00
d11a779fdd
RicE
2008-11-02 03:58:32 -06:00
f092622fac
CFG IR is now pure SSA
2008-10-20 01:56:28 -05:00
c0d89b061e
Fixing register allocator prspilling
2008-10-19 01:10:21 -05:00
7b6d9c4c4f
Debugging new codegen
2008-10-07 20:00:38 -05:00
f436fd0c0f
Merging in new codegen
2008-10-07 16:16:50 -05:00
Slava Pestov
Slava Pestov