4d16c569f0
struct classes now make their own C type without help from alien.structs. remove alien.structs dependencies from everywhere outside of alien and compiler, and have the FFI handle both alien.structs and classes.struct c-types
2009-09-15 17:38:49 -05:00
35b76b83af
convert compiler cpu backends to use c-type words
2009-09-15 16:08:42 -05:00
64cddef3e1
cpu.ppc: fix %single>double-float and %double>single-float
2009-09-10 13:04:58 -05:00
4d1e832f79
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-09 17:14:48 -05:00
c50a35c062
altivec instructions for powerpc assembler
2009-09-09 17:14:36 -05:00
ed09dfe3ae
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-09 13:56:20 -05:00
daff63071f
Fix the build
2009-09-09 13:44:54 -05:00
a01f693335
cpu.ppc: fix bootstrap
2009-09-08 23:53:51 -05:00
0e2a3e4292
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-08 22:34:17 -05:00
cd5133b233
cpu.x86: tweak SIMD intrinsics
2009-09-08 22:34:01 -05:00
f166797dd4
no really, update ppc for argument order changes
2009-09-08 22:21:00 -05:00
3003b9e5d0
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-08 21:58:25 -05:00
c95a7febb0
update cpu.ppc for argument order changes
2009-09-08 21:58:11 -05:00
8916fb7a3c
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-08 21:51:21 -05:00
7e2f0e5dbf
compiler: separate ##save-context instruction from ##alien-invoke, generate a ##save-context for libm calls, and add a pass to combine multiple context saves within a basic block. Fixes crashes with FP traps thrown by libm functions on x86-32
2009-09-08 21:50:55 -05:00
9be1f42fe9
typos in cpu.ppc
2009-09-08 21:44:11 -05:00
410d2bf0d0
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-08 19:35:14 -05:00
74fa73aeaf
Fix various test failures
2009-09-08 19:18:56 -05:00
d02d95ea34
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-08 17:05:58 -05:00
0ea9949e51
split unordered and ordered float comparison intrinsics in compiler; generate only unordered comparisons for now
2009-09-08 17:04:26 -05:00
740a175e56
duplicate using
2009-09-08 17:02:31 -05:00
8b6ec8e030
cpu.x86.features: better wording
2009-09-08 14:17:05 -05:00
e5e7c1f725
cpu.x86.features: add -sse-version command-line switch to override SSE detection
2009-09-08 13:56:37 -05:00
1e5bc3b376
inline alien-vector and set-alien-vector if SIMD is not available for a small speedup
2009-09-08 13:56:17 -05:00
38c961cf6f
Fixes
2009-09-08 00:13:18 -05:00
bbca00e2ae
Fix conflicts
2009-09-07 23:51:25 -05:00
d47d747ebc
i had comisd/ucomisd backwards on x86
2009-09-04 12:30:30 -05:00
382e1d5b0e
fix some typos in cpu.ppc
2009-09-04 11:18:41 -05:00
92d5d8f0c5
Merge branch 'master' of git://factorcode.org/git/factor into ppc-float-compare
2009-09-04 10:58:50 -05:00
638e351131
update powerpc compiler to generate correct float comparisons
2009-09-04 10:51:12 -05:00
fc1bf07a1f
cpu.ppc: fix typo
2009-09-04 06:41:33 -05:00
e36a0d7ef4
compiler: clean up code generation for alien boxing/unboxing a bit
2009-09-03 21:22:43 -05:00
c480bec303
convert comparison branch code in compiler to use locals
2009-09-03 21:19:39 -05:00
4d5a4222b6
More SIMD work
...
- Rename SIMD types and register representations: <type>-<count> rather than <count><type>-array
- Make a functor to define 256-bit vector types, use it to define float-8 type
- Make SIMD instructions pure-insns so that they participate in value numbering
2009-09-03 20:58:56 -05:00
036ff77306
add compiler comparison codes for floating-point unordered comparisons; update x86 backend to generate proper code for all floating-point comparisons
2009-09-03 20:32:05 -05:00
3d4c04302a
Merge branch 'master' into simd
2009-09-03 03:45:58 -05:00
906a0d212a
Detect SSE version and enable the correct set of SIMD intrinsics
2009-09-03 03:28:38 -05:00
ff8c70dbe0
Initial implementation of SSE vector intrinsics:
...
- cpu.architecture: add SSE vector representations
- compiler.cfg.intrinsics.alien: remove an attempt at optimization that value numbering handles now
- compiler.cfg.representations: support instructions where the representation is set in the 'rep' slot, and support conversions between single and double floats
- alien-float, set-alien-float now use the single float representation, and the conversion is implicit; this fixes a long-standing bug where a register could get clobbered because of how %set-alien-float was defined on x86
- math.vectors.specialization: add support for SIMD specialization (where the vector word's body is replaced by another quotation), also specialize the 'sum' word
- math.vectors.simd: 4float-array, 2double-array, 4double-array types, and specializers for the math.vectors words
2009-09-03 02:33:07 -05:00
102df64ec7
i suck at reading tech docs--those were m64 instructions, not mm instructions
2009-09-02 12:58:35 -05:00
962d560c10
get rid of useless mm->xmm instructions in cpu.x86.assembler, add MOVHLPS and MOVLHPS
2009-09-02 11:06:08 -05:00
85a2bfab6c
compiler: eliminate boilerplate by centralizing info in declarative INSN: syntax
2009-09-02 06:22:37 -05:00
f91b539c31
cpu.ppc: implement fast float function calls; 3x speedup on benchmark.struct-arrays on PowerPC
2009-09-01 15:19:26 -05:00
6f1a7c731c
cpu.ppc: fix %box-displaced-alien
2009-08-30 20:56:04 -05:00
9595be4bf9
%box-displaced-alien: fix clobberage found by Doug
2009-08-30 05:11:08 -05:00
0db01f6d5f
compiler.cfg.linear-scan now supports partial sync-points where all registers are spilled; taking advantage of this, there are new trigonometric intrinsics which yield a 2x performance boost on benchmark.struct-arrays and a 25% boost on benchmark.partial-sums
2009-08-30 04:52:01 -05:00
2bb6293217
compiler: add fixnum-min/max intrinsics; ~10% speedup on benchmark.yuv-to-rgb
2009-08-28 19:02:59 -05:00
d957ae4e44
Performance improvements to make struct-arrays benchmark faster
...
- improved optimization of ##unbox-any-c-ptr on ##box-displaced-alien; convert it to ##unbox-c-ptr where possible using class info stored in the ##bda instruction
- make fcos, fsin, etc inline again; everything in math.libm inline again, except for fsqrt which is an intrinsic
- convert min and max on floats to float-min and float-max
- make min and max not inline, so that the above can work
- struct-arrays: rice a bit so that more fixnums come up
2009-08-28 05:21:16 -05:00
98f93f799b
cpu.ppc: fix ##box-displaced-alien
2009-08-27 04:43:45 -05:00
f662e6403a
compiler: new inline intrinsic for <displaced-alien> where the inputs have known types; value numbering now eliminates unnecessary allocation of displaced aliens if the result is immediately unboxed again
2009-08-27 00:06:19 -05:00
0df8aadce2
cpu.x86: use SQRTSD instruction for math.libm:fsqrt word
2009-08-25 23:22:15 -05:00
b7e29ca8dd
cpu.ppc.assembler: LOAD32 assembler macro was busted
2009-08-25 22:37:10 -05:00
1afd001393
basis/cpu: eliminate some usages of rot
2009-08-25 19:38:48 -05:00
7b2c9df341
cpu.ppc.assembler: fix FMR and FMR. opcodes
2009-08-25 19:33:35 -05:00
b14dd8ab67
cpu.ppc: integer>fixnum scratch area overlapped with the rest of stack frame, very bad
2009-08-22 20:23:28 -05:00
2c533472f8
Merge branch 'master' of git://factorcode.org/git/factor
2009-08-21 18:48:44 -05:00
9ab8734441
cpu.ppc: work in progress
2009-08-21 18:48:34 -05:00
3f3d57032b
Delete empty unit tests files, remove 1- and 1+, reorder IN: lines in a lot of places, minor refactoring
2009-08-13 19:21:44 -05:00
4b7ba38aab
compiler.cfg: virtual registers are integers now, and representations are stored off to the side. Fix bug in representation selection that would manifest if a value was used as a float and a fixnum in different branches; cannot globally unbox float in this case
2009-08-08 04:02:18 -05:00
725280d424
Split off the notion of a register representation from a register class
2009-08-07 17:44:50 -05:00
eb3bd1edea
cpu.x86.assembler: make some words private
2009-08-05 18:30:42 -05:00
61fe034e3e
cpu.ppc: put spill slots and GC roots in stack frame where subroutine calls can't clobber them
2009-07-31 23:47:07 -05:00
9a80fdb81b
Merge branch 'master' of git://factorcode.org/git/factor
2009-07-31 17:59:00 -05:00
957a5b7b9b
cpu.ppc: fix small typos
2009-07-31 17:57:15 -05:00
3258f9c4ef
fix using list on win64
2009-07-31 16:27:18 -05:00
dd2dc2bb24
cpu.ppc: Updating PowerPC backend for codegen changes over the last two months: new shift intrinsics added, fixnum overflow intrinsics are now treated like conditionals, GC checks are more complex and have a different API
2009-07-30 21:44:22 -05:00
45770c6250
Move a bunch of GC check generation logic to platform-independent side
2009-07-30 21:28:27 -05:00
b43c8b40ac
Merge branch 'master' of git://factorcode.org/git/factor
2009-07-30 19:11:02 -05:00
b6ddcafcbd
Merge branch 'master' of git://factorcode.org/git/factor
2009-07-30 11:05:36 -05:00
455956b16c
add additional SSE2 packed integer operations
2009-07-30 11:05:12 -05:00
be363d1a5b
compiler.cfg: Get inline GC checks working again, using a dataflow analysis to compute uninitialized stack locations in compiler.cfg.stacks.uninitialized. Re-enable intrinsics which use inline allocation
2009-07-30 09:19:44 -05:00
cd7a1d6c58
Oopsie
2009-07-30 08:27:52 -05:00
d71e2f9577
cpu.x86: Fix shuffle bug. Shuffling bugs occurring in code that runs before optimizer/stack checker is online are only caught at runtime during bootstrap, what a pain
2009-07-30 05:12:40 -05:00
d81dec5d45
cpu.x86: fix a bug in small-register logic on 32-bit. Also, on 32-bit, we don't need to do any special register shuffling to work with 16-bit operands since all registers have 16-bit variants. So now only 8-bit operands on x86-32 require special treatment
2009-07-30 05:04:46 -05:00
a9977d7c79
cpu.x86: update non-optimizing compiler backends for assembler vocab split
2009-07-30 02:22:37 -05:00
1e8d13c1f1
cpu.x86.assembler: fix extended 8-bit registers (DIL, SIL, SPL, BPL)
2009-07-29 22:32:22 -05:00
8ca17d053c
cpu.x86: use full set of 8-bit, 16-bit and 32-bit registers on x86-64 to avoid clumsy save/restore logic
2009-07-29 21:56:37 -05:00
73862a9a03
cpu.x86.assembler: move operands to operands sub-vocabulary, clean up small-reg-* code in compiler backend
2009-07-29 21:44:08 -05:00
09d89c0d17
Merge branch 'dcn'
2009-07-28 12:37:45 -05:00
9f3c8a9959
SSE4 opcodes for x86 assembler
2009-07-28 12:19:37 -05:00
4175585fd4
Merge branch 'master' into dcn
2009-07-28 11:20:43 -05:00
5372113fce
SSE1–SSSE3 opcodes + branch hints for x86 assembler
2009-07-28 00:22:27 -05:00
bfb2a4c1fc
cpu.x86: compile a load of zero, and adds, subs where dst = src1 more efficiently
2009-07-27 22:27:54 -05:00
3fb4fc1bde
Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases
2009-07-16 23:50:48 -05:00
e76dce8aff
Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint
2009-07-16 18:29:40 -05:00
768e2a5148
compiler.cfg: split off condition codes into a comparisons sub-vocabulary
2009-07-13 14:42:52 -05:00
1157f58f37
cpu.x86.32: don't emit sub %esp,0x0 in prologue on Linux and Windows
2009-07-01 18:13:45 -05:00
4db44cd23f
%dispatch: sometimes the generated sequence is one byte longer, so instead of hard-coding it, compute the right length
2009-06-30 18:11:15 -05:00
fc6c9e2dfd
cpu.x86: don't clobber src in %dispatch
2009-06-30 16:47:22 -05:00
45a2105449
cpu.x86.assembler: IMUL2 instruction was busted for immediate operands
...
When given a register and an immediate, it would generate imul imm,dst,dst however the 64-bit prefix was generated wrong and if dst was an extended register only the first operand would be an extended register. To fix this, change IMUL2 to not work on immediates anymore, and added a new IMUL3 that takes a destination register, source register, and immediate. Also, change compiler.cfg.two-operand to not two-operandize %mul-imm, since this isn't needed anymore.
This fixes the sporadic benchmark.tuple-arrays crash on 64-bit machines.
2009-06-08 21:15:52 -05:00
9ad9600764
Remove %dispatch-label since its tehe same on all platforms; fix %gc on PowerPC
2009-06-07 21:46:28 -05:00
49f670be05
Fix 32-bit bootstrap
2009-06-03 03:23:55 -05:00
ade5db2405
cpu.x86: fix small register intrinsics on x86-64
2009-06-03 03:22:46 -05:00
2d231f066a
GC checks now save and restore registers
2009-06-02 18:23:47 -05:00
9e987e8642
Merge branch 'master' into global_optimization
2009-06-01 03:12:32 -05:00
b389dcf441
Redo compiler.codegen.fixup and get %dispatch to work
2009-06-01 02:32:36 -05:00
fc152ef210
Various improvements aimed at getting local optimization regressions fixed:
...
- Rename _gc to ##gc
- Absolute labels are now supported
- Generate _dispatch-label
2009-05-31 23:28:08 -05:00
617e57fc75
cpu.x86.features: add RDTSC support. This is a new vocabulary with words: sse2? instruction-counter count-instructions
2009-05-31 15:02:14 -05:00
76d74c16af
Fixing various bugs; alias analysis wasn't handling ##phi nodes, stack analysis incorrectly handled height-changing back edges and ##fixnum-*, clean up ##dispatch generation
2009-05-29 01:39:14 -05:00
02b769475b
fix duplicate using lines
2009-05-17 20:29:32 -05:00
93509cdcec
Fix cpu.ppc for strict vocabulary search path semantics
2009-05-16 08:58:10 -05:00
Joe Groff
Slava Pestov
Slava Pestov
Doug Coleman
sheeple
Slava Pestov
U-C4\Administrator