152b0d2df5
break simd intrinsics into a separate vocab so they can be intrinsified before the simd methods compile
2009-11-19 11:53:46 -08:00
6583875055
tests for all simd intrinsics
2009-11-18 18:20:58 -08:00
75d04922b9
Merge branch 'master' into simd-cleanup
...
Conflicts:
basis/math/vectors/simd/functor/functor.factor
2009-11-05 11:27:08 -06:00
f6643a1c72
change ##horizontal-add-vector insn to better match what the HADD SSE instructions do (add adjacent pairs, pack results)
2009-11-04 12:18:01 -06:00
51e9a891a8
cpu.x86: update %box-displaced-alien for introduction of address field
2009-11-03 03:17:43 -06:00
b858860a67
add ##shl-vector-imm and ##shr-vector-imm insn variants. use merge/shr instead of compare/merge to do signed unpacks
2009-10-30 00:41:19 -05:00
1e7893b6ce
compiler: FFI is now slightly more efficient when unboxing parameters, only changes data stack height once
2009-10-20 04:31:48 -05:00
2d5cdd19ec
compiler: on PPC, ANDI, ORI and XORI instructions take an unsigned 16-bit immediate, unlike ADDI, SUBI and MULLI which take a signed 16-bit immediate. The code generator was not aware of this, and so for example '[ >fixnum -16 bitand ]' would generate incorrect code. Split up small-enough? hook into immediate-arithmetic? and immediate-bitwise? and update value numbering to be aware of this. Fixes classes.struct bitfields test failure
2009-10-19 04:58:29 -05:00
1ce39963fd
Working on adding support for the new write barrier to optimized code
2009-10-14 02:06:01 -05:00
97ab9dc4ab
only emit ##alien-vector/##set-alien-vector insns if the rep is available
2009-10-10 12:53:10 -05:00
3bc097f6ff
rename ##shuffle-vector to ##shuffle-vector-imm, and add a new ##shuffle-vector for dynamic shuffles. have vshuffle use ##shuffle-vector to do word and byte shuffles on x86
2009-10-09 21:26:27 -05:00
9357ee378e
cpu.architecture: move dummy -reps words here, from cpu.ppc
2009-10-08 03:48:03 -05:00
dd691a61e8
break vector compare intrinsics into %compare, %or, and %not instructions that map directly to cpu instructions
2009-10-07 15:27:03 -05:00
f2c9eb79e2
decompose %unpack-vector-head/tail into %compare-vector/%merge-vector-head/tail or %tail>head-vector/%unpack-vector-head insns when there isn't an actual unpack insn; get rid of fake x86 implementations
2009-10-07 14:09:46 -05:00
879fe9a665
fix x86 %unpack-vector insns
2009-10-06 20:38:51 -05:00
529c444e32
add insns for vector pack, unpack, integer>float, and float>integer
2009-10-05 22:34:14 -05:00
b4e36608da
compiler.cfg: remove _gc instruction, it doesn't need to exist, and change GC checks to ensure that the right amount of space is available instead of blindly checking for 1Kb
2009-10-05 05:27:49 -05:00
0c9c3d4859
add %merge-vector-head and %merge-vector-tail instructions to back vmerge
2009-10-03 21:48:53 -05:00
04bb03bb61
add intrinsics for v<=, v<, v=, v>, v>=, vunordered?
2009-10-03 11:29:34 -05:00
4e024cbbc2
extend x86 %compare-vector to cover all comparison codes, sometimes stupidly for now
2009-10-02 23:19:56 -05:00
38f413a8a6
add intrinsic for vnot/vbitnot
2009-10-02 20:04:28 -05:00
53b265f682
Merge branch 'master' of git://factorcode.org/git/factor
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Conflicts:
basis/compiler/codegen/codegen.factor
2009-10-01 23:14:16 -05:00
f9695951a0
fold test-vector/branch sequences into a test-vector-branch instruction
2009-10-01 19:53:30 -05:00
d14f150b58
%test-vector instruction for vany?, vall?, vnone?
2009-10-01 15:35:38 -05:00
987ced4070
%compare-vector instruction (only does v= for now)
2009-10-01 14:31:37 -05:00
a93f8f66f9
Revert "add a %blend-vector intrinsic for v?"
...
This reverts commit 21e4b28b67
2009-09-30 23:40:37 -05:00
7db7b63552
add a %blend-vector intrinsic for v?
2009-09-30 23:03:59 -05:00
cdc7b7e2c7
Various minor compiler tweaks: Combine address calculation with dereferencing in alien accessors; convert SIMD XOR of a vector with itself into an XOR of the destination with itself; convert SIMD unbox of zero vector into XOR of the destination with itself; fix SIMD indexing on x86-64
2009-09-30 05:00:36 -05:00
f395d83379
math.vectors.simd: add fast intrinsic for 'nth', replace broadcast primitive with shuffles
2009-09-29 04:48:11 -05:00
a8ea929ad9
Work in progress
2009-09-28 17:31:34 -05:00
b2ea3afd84
math.vectors.simd: add hlshift, hrshift (128-bit shift), vbitandn intrinsics
2009-09-28 02:17:46 -05:00
59fbe85c9b
compiler.cfg: nuke ##bignum>integer and ##integer>bignum since they were unused
2009-09-27 20:36:05 -05:00
f757b454cc
Merge branch 'master' into more_aggressive_coalescing
2009-09-27 19:29:50 -05:00
705b4ab5c3
compiler.cfg.linear-scan: fix partial sync point logic in case where dst == src, and clean up spilling code
2009-09-27 19:28:20 -05:00
1e841e5086
compiler.cfg.ssa.destruction: more aggressive coalescing work in progress
2009-09-27 17:17:26 -05:00
01a4047126
Merge branch 'slots' of git://factorcode.org/git/factor into slots
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Conflicts:
basis/cpu/x86/x86.factor
2009-09-26 03:12:42 -05:00
51f2bbd74b
Completing slot and set-slot changes on x86
2009-09-26 01:39:48 -05:00
d457df1fbf
moved %(un)nest-stacks out to cpu specific files to eliminate %vm-invoke from compiler.codegen
2009-09-25 19:32:08 +01:00
28420c587a
isolated %vm-invoke-blah-arg crap to 64.factor
2009-09-25 19:02:41 +01:00
a07a2f7496
compiler.codegen passes temp reg to %call-gc
2009-09-25 18:48:13 +01:00
7b6128dd03
math.vectors.simd: add v<< and v>> intrinsics for bitwise shifts on elements
2009-09-24 03:32:39 -05:00
dfc9fd071e
Add longlong-2, ulonglong-2, longlong-4, ulonglong-4 SIMD types, fix int-4 multiplication on SSE2
2009-09-23 20:23:25 -05:00
43fa252af5
math.vectors.simd: new operations: vabs vsqrt vbitand vbitor vbitxor
2009-09-23 02:47:14 -05:00
9d90bdd439
Fix conflict
2009-09-20 23:18:07 -05:00
ea44ea3522
math.vectors.simd: add saturated arithmetic operations
2009-09-20 23:16:02 -05:00
acea55c692
math.vectors: add v+- word which is accelerated by SSE3
2009-09-20 17:43:16 -05:00
e77341b90c
math.vectors.simd: redesign to be more flexible, integer SIMD work in progress
2009-09-20 02:08:32 -05:00
0bc7c0c1d0
separated vm-1st-arg and vm-3rd-arg asm invoke words (needed for ppc & x86.64)
2009-09-16 08:20:09 +01:00
ff54a57eb3
added code to pass vm ptr to some unboxers
2009-09-16 08:16:32 +01:00
ff8f2b10ec
fixed up getenv compiler intrinsic to use vm struct userenv
2009-09-16 08:16:32 +01:00
6a193bb0d5
Added %vm-invoke to pass vm ptr to vm functions (x86.32 only, otherwise uses singleton vm)
2009-09-16 08:16:30 +01:00
7e2f0e5dbf
compiler: separate ##save-context instruction from ##alien-invoke, generate a ##save-context for libm calls, and add a pass to combine multiple context saves within a basic block. Fixes crashes with FP traps thrown by libm functions on x86-32
2009-09-08 21:50:55 -05:00
0ea9949e51
split unordered and ordered float comparison intrinsics in compiler; generate only unordered comparisons for now
2009-09-08 17:04:26 -05:00
1e5bc3b376
inline alien-vector and set-alien-vector if SIMD is not available for a small speedup
2009-09-08 13:56:17 -05:00
e36a0d7ef4
compiler: clean up code generation for alien boxing/unboxing a bit
2009-09-03 21:22:43 -05:00
4d5a4222b6
More SIMD work
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- Rename SIMD types and register representations: <type>-<count> rather than <count><type>-array
- Make a functor to define 256-bit vector types, use it to define float-8 type
- Make SIMD instructions pure-insns so that they participate in value numbering
2009-09-03 20:58:56 -05:00
ff8c70dbe0
Initial implementation of SSE vector intrinsics:
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- cpu.architecture: add SSE vector representations
- compiler.cfg.intrinsics.alien: remove an attempt at optimization that value numbering handles now
- compiler.cfg.representations: support instructions where the representation is set in the 'rep' slot, and support conversions between single and double floats
- alien-float, set-alien-float now use the single float representation, and the conversion is implicit; this fixes a long-standing bug where a register could get clobbered because of how %set-alien-float was defined on x86
- math.vectors.specialization: add support for SIMD specialization (where the vector word's body is replaced by another quotation), also specialize the 'sum' word
- math.vectors.simd: 4float-array, 2double-array, 4double-array types, and specializers for the math.vectors words
2009-09-03 02:33:07 -05:00
85a2bfab6c
compiler: eliminate boilerplate by centralizing info in declarative INSN: syntax
2009-09-02 06:22:37 -05:00
9595be4bf9
%box-displaced-alien: fix clobberage found by Doug
2009-08-30 05:11:08 -05:00
0db01f6d5f
compiler.cfg.linear-scan now supports partial sync-points where all registers are spilled; taking advantage of this, there are new trigonometric intrinsics which yield a 2x performance boost on benchmark.struct-arrays and a 25% boost on benchmark.partial-sums
2009-08-30 04:52:01 -05:00
2bb6293217
compiler: add fixnum-min/max intrinsics; ~10% speedup on benchmark.yuv-to-rgb
2009-08-28 19:02:59 -05:00
d957ae4e44
Performance improvements to make struct-arrays benchmark faster
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- improved optimization of ##unbox-any-c-ptr on ##box-displaced-alien; convert it to ##unbox-c-ptr where possible using class info stored in the ##bda instruction
- make fcos, fsin, etc inline again; everything in math.libm inline again, except for fsqrt which is an intrinsic
- convert min and max on floats to float-min and float-max
- make min and max not inline, so that the above can work
- struct-arrays: rice a bit so that more fixnums come up
2009-08-28 05:21:16 -05:00
f662e6403a
compiler: new inline intrinsic for <displaced-alien> where the inputs have known types; value numbering now eliminates unnecessary allocation of displaced aliens if the result is immediately unboxed again
2009-08-27 00:06:19 -05:00
0df8aadce2
cpu.x86: use SQRTSD instruction for math.libm:fsqrt word
2009-08-25 23:22:15 -05:00
4b7ba38aab
compiler.cfg: virtual registers are integers now, and representations are stored off to the side. Fix bug in representation selection that would manifest if a value was used as a float and a fixnum in different branches; cannot globally unbox float in this case
2009-08-08 04:02:18 -05:00
725280d424
Split off the notion of a register representation from a register class
2009-08-07 17:44:50 -05:00
45770c6250
Move a bunch of GC check generation logic to platform-independent side
2009-07-30 21:28:27 -05:00
be363d1a5b
compiler.cfg: Get inline GC checks working again, using a dataflow analysis to compute uninitialized stack locations in compiler.cfg.stacks.uninitialized. Re-enable intrinsics which use inline allocation
2009-07-30 09:19:44 -05:00
3fb4fc1bde
Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases
2009-07-16 23:50:48 -05:00
e76dce8aff
Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint
2009-07-16 18:29:40 -05:00
9ad9600764
Remove %dispatch-label since its tehe same on all platforms; fix %gc on PowerPC
2009-06-07 21:46:28 -05:00
2d231f066a
GC checks now save and restore registers
2009-06-02 18:23:47 -05:00
b389dcf441
Redo compiler.codegen.fixup and get %dispatch to work
2009-06-01 02:32:36 -05:00
fc152ef210
Various improvements aimed at getting local optimization regressions fixed:
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- Rename _gc to ##gc
- Absolute labels are now supported
- Generate _dispatch-label
2009-05-31 23:28:08 -05:00
76d74c16af
Fixing various bugs; alias analysis wasn't handling ##phi nodes, stack analysis incorrectly handled height-changing back edges and ##fixnum-*, clean up ##dispatch generation
2009-05-29 01:39:14 -05:00
c93d876075
Better separation of concerns: cpu.{x86,ppc}.assembler no longer depends on compiler.codegen.fixup and cpu.architecture. Rename rt-xt-direct to rt-xt-pic to better explain its purpose
2009-05-06 16:14:53 -05:00
facd455e92
Working on complex float support in FFI on NetBSD
2009-02-12 06:25:07 -06:00
44bfff7c7b
Rename ##load-indirect to ##load-reference since this is more descriptive; value numbering doesn't assign expressions to ##load-reference nodes since this would end up folding literals which were eq? but not =
2009-01-29 01:44:58 -06:00
8a8f0c925c
Use BSR instruction to implement fixnum-log2 intrinsic
2008-12-06 15:31:17 -06:00
a56d480aa6
Various optimizations leading to a 10% speedup on compiling empty EBNF parser:
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- open-code getenv primitive
- inline tuple predicates in finalization
- faster partial dispatch
- faster built-in type predicates
- faster tuple predicates
- faster lo-tag dispatch
- compile V{ } clone and H{ } clone more efficiently
- add fixnum fast-path to =; avoid indirect branch if two fixnums not eq
- faster >alist on hashtables
2008-12-06 09:16:29 -06:00
e256846acd
Tweak string representation; high bit indicates if character has high bits in aux vector. Avoids memory access in common case. Split set-string-nth into two primitives; set-string-nth-fast is open-coded by optimizing compiler. 13% improvement on reverse-complement
2008-12-05 06:38:51 -06:00
e7f4563374
fixnum* intrinsic for x86
2008-11-30 07:26:49 -06:00
f44506089d
More work on overflow instructions: don't need temp register anymore, add -tail variants which don't need stack frame
2008-11-28 06:36:30 -06:00
5634becda1
##fixnum-add, ##fixnum-sub instructions open-code overflow check
2008-11-28 05:33:58 -06:00
ab689c098b
Clean up direct literal code and make a first attempt at PowerPC support
2008-11-24 08:16:14 -06:00
20f5541d35
Refactoring FFI for Win64
2008-11-17 13:34:37 -06:00
eb05dd3a12
Optimize a ##dispatch that is applied to the result of a ##sub-imm or ##add-imm; this eliminates an instruction from the common 1 fixnum-fast { ... } dispatch and 8 fixnum-fast { ... } dispatch code sequences appearing in generic word expansions
2008-11-13 04:16:08 -06:00
f7fe84e563
Working on Win64 FFI
2008-11-08 21:40:47 -06:00
53cd75b06c
Add string-nth intrinsic
2008-11-06 01:11:28 -06:00
dae41147fe
%bignum>integer now takes a temporary register since this is useful on both x86 and ppc
2008-11-05 04:16:08 -06:00
59f4f25b91
Loop alignment: appears to be a small win for reverse-complement
2008-11-03 06:20:51 -06:00
db4db19cd9
Start working on coalescing
2008-10-28 02:38:37 -07:00
87e9fbb34c
Comparison operations
2008-10-21 03:21:29 -05:00
e92f795a76
More work on intrinsics; memory allocation and slot access now expands correctly
2008-10-20 20:40:15 -05:00
37cf7d9a9c
Add SSA comparison instructions, fix various problems
2008-10-20 05:55:20 -05:00
f092622fac
CFG IR is now pure SSA
2008-10-20 01:56:28 -05:00
774ecf61e9
Implement spilling on x86
2008-10-19 01:10:45 -05:00
d8d3645d72
Fixing more codegen bugs
2008-10-13 12:49:20 -05:00
ae3c4ae1b6
Fix some problems with callbacks
2008-10-12 23:32:14 -05:00
3844cb62d8
Fix %write-barrier
2008-10-10 03:16:26 -05:00
cf46a832e7
Debugging register allocator and inline allocation
2008-10-08 23:42:53 -05:00
0e4e05d5cd
Debugging new codegen
2008-10-08 03:51:44 -05:00
7b6d9c4c4f
Debugging new codegen
2008-10-07 20:00:38 -05:00
e6e313eba9
Backend updates
2008-10-07 16:42:11 -05:00
e69278b8fc
Merging in new codegen
2008-10-07 16:17:55 -05:00
33d775890c
More stack frame refactoring
2008-10-06 00:20:00 -05:00
c19f2257f4
Fix permission bits
2008-10-02 08:34:49 -05:00
722cacddb4
Fixing some problems with returning structs by value in x86.64 FFI
2008-09-13 20:28:13 -05:00
44f53de164
Move make to its own vocabulary, remove fry _ feature
2008-09-10 20:07:00 -05:00
a3d1379b8c
Fix bug with large structs passed by value on x86.64
2008-09-09 03:10:43 -05:00
86f11713e3
Fixing some more bugs
2008-08-22 03:12:15 -05:00
d66f887736
Create basis vocab root
2008-07-28 22:03:13 -05:00
Joe Groff
Slava Pestov
Slava Pestov
sheeple
Daniel Ehrenberg
Phil Dawes
Slava Pestov
sheeple
unknown