2517b2fc2b
compiler: combine ##load-constant followed by ##alien-double into a ##load-double on x86-32, saving an integer register
2010-04-18 21:42:45 -05:00
eceabbc57e
compiler: new set-special-object intrinsic; more efficient special-object intrinsic
2010-04-01 20:09:14 -04:00
d98e752199
compiler: add intrinsic for context-object primitive
2010-03-27 02:56:11 -04:00
235f3238f5
Add alien-assembly form for inline assembler, works like alien-invoke except calls a user-supplied quotation instead of generating a subroutine call. Replaces FPU status control, SSE detection and read timestamp routines in vm/cpu-x86.*S
2010-01-07 17:39:22 +13:00
ba5b90e063
Change how non-volatile register preservation is done in alien callbacks, with the aim of fixing callbacks on PowerPC, and to eventually eliminate assembly code from VM
...
- Simplify calculation of offset in relocation table
- Open-code %alien-callback
- Remove magic_frame hack from context objects
- Move magical return instruction from optimizing compiler backend into callback entry stub
2010-01-03 01:11:51 +13:00
e96404327e
Get optimizing compiler working without global register variables in VM
2009-12-22 15:42:49 +13:00
104c29aabc
simd intrinsic implementation for v*high, v*hs+, vavg, and vsad
2009-12-05 14:52:18 -08:00
75d04922b9
Merge branch 'master' into simd-cleanup
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Conflicts:
basis/math/vectors/simd/functor/functor.factor
2009-11-05 11:27:08 -06:00
f6643a1c72
change ##horizontal-add-vector insn to better match what the HADD SSE instructions do (add adjacent pairs, pack results)
2009-11-04 12:18:01 -06:00
51e9a891a8
cpu.x86: update %box-displaced-alien for introduction of address field
2009-11-03 03:17:43 -06:00
e4ad642134
vm: 4 bit tags, new representation of alien objects makes unbox-any-c-ptr more efficient (work in progress)
2009-11-02 04:25:54 -06:00
b858860a67
add ##shl-vector-imm and ##shr-vector-imm insn variants. use merge/shr instead of compare/merge to do signed unpacks
2009-10-30 00:41:19 -05:00
bd13e018dd
memq? -> member-eq?, sorted-memq? -> sorted-member-eq?
2009-10-28 15:02:00 -05:00
1ce39963fd
Working on adding support for the new write barrier to optimized code
2009-10-14 02:06:01 -05:00
3bc097f6ff
rename ##shuffle-vector to ##shuffle-vector-imm, and add a new ##shuffle-vector for dynamic shuffles. have vshuffle use ##shuffle-vector to do word and byte shuffles on x86
2009-10-09 21:26:27 -05:00
dd691a61e8
break vector compare intrinsics into %compare, %or, and %not instructions that map directly to cpu instructions
2009-10-07 15:27:03 -05:00
f2c9eb79e2
decompose %unpack-vector-head/tail into %compare-vector/%merge-vector-head/tail or %tail>head-vector/%unpack-vector-head insns when there isn't an actual unpack insn; get rid of fake x86 implementations
2009-10-07 14:09:46 -05:00
34def34481
don't generate a ##not-vector instruction if the cpu doesn't have one; instead, fall back to a ##fill-vector/##xor-vector combo. get rid of pretend %not-vector in cpu.x86
2009-10-07 11:59:36 -05:00
879fe9a665
fix x86 %unpack-vector insns
2009-10-06 20:38:51 -05:00
529c444e32
add insns for vector pack, unpack, integer>float, and float>integer
2009-10-05 22:34:14 -05:00
b4e36608da
compiler.cfg: remove _gc instruction, it doesn't need to exist, and change GC checks to ensure that the right amount of space is available instead of blindly checking for 1Kb
2009-10-05 05:27:49 -05:00
0c9c3d4859
add %merge-vector-head and %merge-vector-tail instructions to back vmerge
2009-10-03 21:48:53 -05:00
4e024cbbc2
extend x86 %compare-vector to cover all comparison codes, sometimes stupidly for now
2009-10-02 23:19:56 -05:00
38f413a8a6
add intrinsic for vnot/vbitnot
2009-10-02 20:04:28 -05:00
bcbdc9e0c8
Merge branch 'master' of git://factorcode.org/git/factor into improved-aa
2009-10-02 00:21:44 -05:00
53b265f682
Merge branch 'master' of git://factorcode.org/git/factor
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Conflicts:
basis/compiler/codegen/codegen.factor
2009-10-01 23:14:16 -05:00
31f39ce32f
compiler.cfg.alias-analysis: optimize ##vm-field-ptr and ##alien-global instructions, and optimize out ##compare between values of different alias classes; this optimizes '[ [ >float ] bi@ [ + ] [ - ] 2bi eq? ]' down to an o-op and removes boxing from '[ [ >float ] bi@ [ + ] [ - ] 2bi = ]'
2009-10-01 23:03:17 -05:00
f9695951a0
fold test-vector/branch sequences into a test-vector-branch instruction
2009-10-01 19:53:30 -05:00
b9577e2b0e
compiler.cfg.instructions: remove ##box-float, ##unbox-float, ##box-vector, ##unbox-vector since they can be expressed in terms of ##alien-double, ##set-alien-double, ##alien-vector, ##set-alien-vector, and ##allot
2009-10-01 18:07:50 -05:00
d14f150b58
%test-vector instruction for vany?, vall?, vnone?
2009-10-01 15:35:38 -05:00
987ced4070
%compare-vector instruction (only does v= for now)
2009-10-01 14:31:37 -05:00
a93f8f66f9
Revert "add a %blend-vector intrinsic for v?"
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This reverts commit 21e4b28b67
2009-09-30 23:40:37 -05:00
67cc45235d
Merge branch 'master' of git://factorcode.org/git/factor
2009-09-30 23:04:04 -05:00
7db7b63552
add a %blend-vector intrinsic for v?
2009-09-30 23:03:59 -05:00
2384b630b2
math.vectors.simd: use fallbacks for hlshift, hrshift, vshuffle if parameter is not a literal;al; element access in int-4 on x86-64 now sign-extends the value; don't throw error at compile time if parameter for vshuffle does not have enough elements
2009-09-30 20:04:37 -05:00
cdc7b7e2c7
Various minor compiler tweaks: Combine address calculation with dereferencing in alien accessors; convert SIMD XOR of a vector with itself into an XOR of the destination with itself; convert SIMD unbox of zero vector into XOR of the destination with itself; fix SIMD indexing on x86-64
2009-09-30 05:00:36 -05:00
1da18d06b1
compiler.cfg.value-numbering: add some more rewrite rules, neg/neg, not/not, and a few for SIMD
2009-09-30 02:18:29 -05:00
f395d83379
math.vectors.simd: add fast intrinsic for 'nth', replace broadcast primitive with shuffles
2009-09-29 04:48:11 -05:00
a8ea929ad9
Work in progress
2009-09-28 17:31:34 -05:00
b2ea3afd84
math.vectors.simd: add hlshift, hrshift (128-bit shift), vbitandn intrinsics
2009-09-28 02:17:46 -05:00
59fbe85c9b
compiler.cfg: nuke ##bignum>integer and ##integer>bignum since they were unused
2009-09-27 20:36:05 -05:00
66071f45a3
Add a couple more def-is-use instructions
2009-09-27 20:34:20 -05:00
f757b454cc
Merge branch 'master' into more_aggressive_coalescing
2009-09-27 19:29:50 -05:00
705b4ab5c3
compiler.cfg.linear-scan: fix partial sync point logic in case where dst == src, and clean up spilling code
2009-09-27 19:28:20 -05:00
1e841e5086
compiler.cfg.ssa.destruction: more aggressive coalescing work in progress
2009-09-27 17:17:26 -05:00
01a4047126
Merge branch 'slots' of git://factorcode.org/git/factor into slots
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Conflicts:
basis/cpu/x86/x86.factor
2009-09-26 03:12:42 -05:00
7bd330cfd5
Making ##slot and ##set-slot not have a temporary parameter
2009-09-26 00:28:14 -05:00
cb497f009b
Merge branch 'vm_cleanup' of git://github.com/phildawes/factor
2009-09-24 04:31:55 -05:00
7b6128dd03
math.vectors.simd: add v<< and v>> intrinsics for bitwise shifts on elements
2009-09-24 03:32:39 -05:00
84faf2431f
cleaned up vm-field-ptr compiler code
2009-09-24 08:16:57 +01:00
43fa252af5
math.vectors.simd: new operations: vabs vsqrt vbitand vbitor vbitxor
2009-09-23 02:47:14 -05:00
9d90bdd439
Fix conflict
2009-09-20 23:18:07 -05:00
ea44ea3522
math.vectors.simd: add saturated arithmetic operations
2009-09-20 23:16:02 -05:00
acea55c692
math.vectors: add v+- word which is accelerated by SSE3
2009-09-20 17:43:16 -05:00
ff8f2b10ec
fixed up getenv compiler intrinsic to use vm struct userenv
2009-09-16 08:16:32 +01:00
7e2f0e5dbf
compiler: separate ##save-context instruction from ##alien-invoke, generate a ##save-context for libm calls, and add a pass to combine multiple context saves within a basic block. Fixes crashes with FP traps thrown by libm functions on x86-32
2009-09-08 21:50:55 -05:00
0ea9949e51
split unordered and ordered float comparison intrinsics in compiler; generate only unordered comparisons for now
2009-09-08 17:04:26 -05:00
e36a0d7ef4
compiler: clean up code generation for alien boxing/unboxing a bit
2009-09-03 21:22:43 -05:00
4d5a4222b6
More SIMD work
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- Rename SIMD types and register representations: <type>-<count> rather than <count><type>-array
- Make a functor to define 256-bit vector types, use it to define float-8 type
- Make SIMD instructions pure-insns so that they participate in value numbering
2009-09-03 20:58:56 -05:00
ff8c70dbe0
Initial implementation of SSE vector intrinsics:
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- cpu.architecture: add SSE vector representations
- compiler.cfg.intrinsics.alien: remove an attempt at optimization that value numbering handles now
- compiler.cfg.representations: support instructions where the representation is set in the 'rep' slot, and support conversions between single and double floats
- alien-float, set-alien-float now use the single float representation, and the conversion is implicit; this fixes a long-standing bug where a register could get clobbered because of how %set-alien-float was defined on x86
- math.vectors.specialization: add support for SIMD specialization (where the vector word's body is replaced by another quotation), also specialize the 'sum' word
- math.vectors.simd: 4float-array, 2double-array, 4double-array types, and specializers for the math.vectors words
2009-09-03 02:33:07 -05:00
85a2bfab6c
compiler: eliminate boilerplate by centralizing info in declarative INSN: syntax
2009-09-02 06:22:37 -05:00
9595be4bf9
%box-displaced-alien: fix clobberage found by Doug
2009-08-30 05:11:08 -05:00
0db01f6d5f
compiler.cfg.linear-scan now supports partial sync-points where all registers are spilled; taking advantage of this, there are new trigonometric intrinsics which yield a 2x performance boost on benchmark.struct-arrays and a 25% boost on benchmark.partial-sums
2009-08-30 04:52:01 -05:00
2bb6293217
compiler: add fixnum-min/max intrinsics; ~10% speedup on benchmark.yuv-to-rgb
2009-08-28 19:02:59 -05:00
d957ae4e44
Performance improvements to make struct-arrays benchmark faster
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- improved optimization of ##unbox-any-c-ptr on ##box-displaced-alien; convert it to ##unbox-c-ptr where possible using class info stored in the ##bda instruction
- make fcos, fsin, etc inline again; everything in math.libm inline again, except for fsqrt which is an intrinsic
- convert min and max on floats to float-min and float-max
- make min and max not inline, so that the above can work
- struct-arrays: rice a bit so that more fixnums come up
2009-08-28 05:21:16 -05:00
8f19f14c1f
compiler.cfg.instructions: forgot that ##box-displaced-alien needs a GC check; fixes segfault in benchmark.mandel
2009-08-27 04:09:35 -05:00
f662e6403a
compiler: new inline intrinsic for <displaced-alien> where the inputs have known types; value numbering now eliminates unnecessary allocation of displaced aliens if the result is immediately unboxed again
2009-08-27 00:06:19 -05:00
0df8aadce2
cpu.x86: use SQRTSD instruction for math.libm:fsqrt word
2009-08-25 23:22:15 -05:00
cc5476c823
_gc instruction doesn't need slot to hold GC root area size, since that's just tagged-values>> length
2009-08-09 03:08:13 -05:00
e21ca289c3
compiler.cfg.representations: new pass to make global unboxing decisions, relies on new compiler.cfg.loop-detection pass for loop nesting information
2009-08-08 00:24:46 -05:00
725280d424
Split off the notion of a register representation from a register class
2009-08-07 17:44:50 -05:00
be363d1a5b
compiler.cfg: Get inline GC checks working again, using a dataflow analysis to compute uninitialized stack locations in compiler.cfg.stacks.uninitialized. Re-enable intrinsics which use inline allocation
2009-07-30 09:19:44 -05:00
cb7735ddf4
compiler.cfg: remove 'regs' slot from instruction tuples now that register allocation doesn't use it anymore
2009-07-29 06:50:46 -05:00
74766d1ccd
compiler.cfg.linear-scan.assignment: modifies instructions in place instead of storing a registers assoc for further compile-time performance improvement
2009-07-29 06:36:14 -05:00
3cc71a1934
compiler.cfg.coalescing: precompute live intervals, add support for instructions where output cannot equal an input, split critical edges
2009-07-27 22:29:17 -05:00
d947c61bd7
compiler.cfg.stacks: now performs online local DCN
2009-07-23 20:54:38 -05:00
44bcd258f6
Insert _loop-entry in linearization pass instead of in CFG builder, so that optimizations don't have to worry about it
2009-07-22 06:05:17 -05:00
fdef772d67
compiler.cfg: if a block has an instruction that kills values it must be the only instruction in the block
2009-07-19 20:12:04 -05:00
605b37a949
compiler.cfg.builder: annotate calls with height changes, once again
2009-07-18 23:08:53 -05:00
3fb4fc1bde
Improve code generation for shift word: add intrinsics for fixnum-shift-fast in the case where the shift count is not constant, transform 1 swap shift into a more overflow check with open-coded fast case, transform bitand into fixnum-bitand in more cases
2009-07-16 23:50:48 -05:00
e76dce8aff
Overflowing fixnum intrinsics now expand into several CFG nodes. This speeds up the common case since only the uncommon case is now a stack syncpoint
2009-07-16 18:29:40 -05:00
9f926ab88c
compiler.cfg.block-joining: join basic blocks connected by a single edge to improve effectiveness of local optimizations
2009-07-16 02:17:58 -05:00
768e2a5148
compiler.cfg: split off condition codes into a comparisons sub-vocabulary
2009-07-13 14:42:52 -05:00
a452f32e3a
compiler.cfg.linear-scan: Get cycle breaking in resolve pass to work by allocating a spare spill slot for this purpose
2009-07-05 21:32:23 -05:00
fb488025aa
compiler.cfg.value-numbering.rewrite: fix ##compare-imm rewrite rule
2009-07-04 02:50:50 -05:00
da13681bc8
compiler.cfg.linear-scan: redo resolve pass to fix a correctness issue
2009-07-03 23:38:52 -05:00
8d3a45dee2
compiler.cfg: clean up GC check generation to use spill-slot data type
2009-07-03 23:11:23 -05:00
af875ba836
compiler.cfg: bug fixes in GC check insertion and fixnum intrinsics
2009-07-02 00:51:06 -05:00
0402790001
compiler.cfg Remove height tracking for ##call instructions, wire in ##no-tco instruction
2009-06-30 21:21:46 -05:00
d1f6871081
fix bug where traversal order was lost
2009-06-30 16:44:14 -05:00
90017eb248
add spill-temp to compiler.cfg.instructions, implement parallel register assignment in linear-scan.resolve
2009-06-26 21:48:21 -05:00
d0f6a7d048
Split up compiler.cfg.linear-scan.allocation into a number of sub-vocabularies; start work on compiler.cfg.linear-scan.resolve; start work on inactive interval splitting
2009-06-11 17:55:14 -05:00
2d231f066a
GC checks now save and restore registers
2009-06-02 18:23:47 -05:00
1a52414bb1
Rename _gc to ##gc
2009-05-31 18:21:11 -05:00
e04df76f60
Various codegen improvements:
...
- new-insn word to construct instructions
- cache RPO in the CFG
- re-organize low-level optimizer so that MR is built after register allocation
- register allocation now stores instruction numbers in the instructions themselves
- split defs-vregs into defs-vregs and temp-vregs
2009-05-29 13:11:34 -05:00
743550f19c
Put GC checks in the right place when linearizing, and generate _dispatch-labels
2009-05-29 05:36:04 -05:00
76d74c16af
Fixing various bugs; alias analysis wasn't handling ##phi nodes, stack analysis incorrectly handled height-changing back edges and ##fixnum-*, clean up ##dispatch generation
2009-05-29 01:39:14 -05:00
3b79d61496
Add a new ##allocation union to remove some code duplication
2009-05-27 18:55:49 -05:00
1db81da264
Refactoring low-level optimizer to support stack analysis pass
2009-05-26 19:31:19 -05:00
6af61656f3
CFG optimizer work in progress - adding phi nodes
2009-05-21 16:49:28 -05:00
Slava Pestov
Joe Groff
Doug Coleman
Slava Pestov
sheeple
Daniel Ehrenberg
Phil Dawes